A system, method, and computer program product are provided for a memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.

System, method, and computer program product for improving memory systems

Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5D- and 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5D- and 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this paper, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access.

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Due to the prohibitive costs of semiconductor manufacturing, most system-on-chip design companies outsource their production to offshore foundries. As most of these devices are manufactured in environments of limited trust that often lack appropriate oversight, a number of different threats have emerged. These include unauthorized overproduction of the integrated circuits (ICs), sale of out-of-specification/rejected ICs discarded by manufacturing tests, piracy of intellectual property, and reverse engineering of the designs. Over the years, researchers have proposed different metering and obfuscation techniques to enable trust in outsourced IC manufacturing, where the design is obfuscated by modifying the underlying functionality and only activated by using a secure obfuscation key. However, Boolean satisfiability-based algorithms have been shown to efficiently break key-based obfuscation methods, and thus circumvent the primary objectives of metering and obfuscation. In this paper, we present a novel secure cell design for implementing the design-for-security infrastructure to prevent leaking the key to an adversary under any circumstances. Importantly, our design does not limit the testability of the chip during the normal manufacturing flow in any way, including postsilicon validation and debug. Our proposed design is resistant to various known attacks at the cost of a very little (< 1%) area overhead.

Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test

Currently, medical image segmentation has attracted more attention from researchers, which can assist in medical diagnosis. However, in the process of traditional medical image segmentation, it is sensitive to the initial contour and noise, which is difficult to deal with the weak edge image, complex iterative process. In this paper, we propose a new medical image segmentation method, which adopts density-oriented BIRCH (balanced iterative reducing and clustering using hierarchies) clustering method to modify active contour model and improve the robustness of noise. The BIRCH is a multi-stage clustering method using clustering feature tree. The improved model can effectively deal with the gray non-uniformity of real medical images. And we also introduce a new energy function in active contour model to make the contour curve approach to the edge, and finally stay at the edge of the image to complete the object segmentation. Experimental results show that this new model can overcome the influence of complex background on medical image segmentation and improve the speed and accuracy of medical segmentation results.

Active contour modal based on density-oriented BIRCH clustering method for medical image segmentation

Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs are now being studied in the research community, and experts in industry have identified a number of hard problems related to the lack of probe access for wafers, test access in stacked dies, yield enhancement, and new defects arising from unique processing steps. We describe a number of testing and DfT challenges, and present some of the solutions being advocated for these challenges. Techniques highlighted in this paper include: (i) pre-bond testing of TSVs and die logic, including probing and non-invasive test using DfT; (ii) post-bond testing and DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow selection.

Test and Design-for-Testability Solutions for 3D Integrated Circuits

Three-dimensional Stacked Integrated Circuit packages interconnected using high speed Through-Silicon Via technology can be efficiently manufactured using a wafer-to-wafer stacking process. Efforts to mitigate degradation in the composite yield of the stacked die are primarily focused on matching defect maps while assigning the pre-tested wafers from the available wafer repository to individual wafer stacks. In this paper we show how rotational symmetry can be exploited to increase the number of available wafer defect maps by a factor of four, thereby significantly improving matching possibilities and hence yield. We further apply our approach to processor-memory stacks, with relatively high memory die yield from redundancy and repair, for which we also present new heuristic matching algorithms. Altogether, our new approach shows viable absolute yields, with yield improvement of better than 25% over stacking without any matching. This is a significant advance over earlier results.

Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs

During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing post-silicon validation and debug techniques are mostly ad hoc and often involve manual steps. Such ad hoc approaches cannot scale with increasing IC complexity. We present Symbolic Quick Error Detection (Symbolic QED), a structured approach to post-silicon validation and debug. Symbolic QED combines the following steps in a coordinated fashion: 1. Quick Error Detection (QED) tests that quickly detect bugs with short error detection latencies and high coverage. 2. Formal analysis techniques to localize bugs and generate minimal-length bug traces upon detection of the corresponding bugs. We demonstrate the practicality and effectiveness of Symbolic QED using the OpenSPARC T2, a 500-million-transistor open-source multicore System-on-Chip (SoC) design, and using "difficult" logic bug scenarios that occurred in various state-of-the-art commercial multicore SoCs. Our results show that Symbolic QED: (i) is fully automatic (unlike manual techniques in use today that can be extremely time-consuming and expensive); (ii) requires only a few hours in contrast to manual approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs; (iii) generates counter-examples (for activating and detecting logic bugs) that are up to 6 orders of magnitude shorter than those produced by traditional techniques; and, (iv) does not require any additional hardware.

A structured approach to post-silicon validation and debug using symbolic quick error detection

We present and evaluate a simulation methodology to model the impact of the radial clustering of defects on wafers on the yield of 3D ICs manufactured using wafer to wafer stacking. Our simulations draw on an extensively validated model for radial yield degradation on wafers from the literature to incorporate the effect of this key contributor to the widely observed clustering of defects on semiconductor wafers. Current 3D-SIC yield estimation methods ignore defect clustering and assume a uniform distribution of defective dies on each wafer. Our results show that the radial clustering of defective dies causes stacked die yields to be significantly higher than that projected by current models. For 4–5 layer stacks the difference can be 50% or more. Our simulation studies are further validated by comparison with actual silicon data, which suggests that even the more accurate yield estimates from our improved methodology may be somewhat pessimistic. Thus the results presented here show that in practice degradation in stacked die yield from compounding may not be as severe as commonly estimated. This has significant implications in evaluating cost trade-offs associated with 3D-SIC manufacturing.

Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking

We present Symbolic Quick Error Detection (Symbolic QED), a structured approach for logic bug detection and localization which can be used both during pre-silicon design verification as well as post-silicon validation and debug. This new methodology leverages prior work on Quick Error Detection (QED) which has been demonstrated to drastically reduce the latency, in terms of the number of clock cycles, of error detection following the activation of a logic (or electrical) bug. QED works through software transformations, including redundant execution and control flow checking, of the applied tests. Symbolic QED combines these error-detecting QED transformations with bounded model checking-based formal analysis to generate minimal-length bug activation traces that detect and localize any logic bugs in the design. We demonstrate the practicality and effectiveness of Symbolic QED using the OpenSPARC T2, a 500-million-transistor open-source multicore System-on-Chip (SoC) design, and using “difficult” logic bug scenarios observed in various state-of-the-art commercial multicore SoCs. Our results show that Symbolic QED: (i) is fully automatic, unlike manual techniques in use today that can be extremely time-consuming and expensive; (ii) requires only a few hours in contrast to manual approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs; and (iii) generates counter-examples (for activating and detecting logic bugs) that are up to 6 orders of magnitude shorter than those produced by traditional techniques. Significantly, this new approach does not require any additional hardware.

Logic Bug Detection and Localization Using Symbolic Quick Error Detection

We present A-QED (Accelerator-Quick Error Detection), a new approach for pre-silicon formal verification of stand-alone hardware accelerators. A-QED relies on bounded model checking -- however, it does not require extensive design-specific properties or a full formal design specification. While A- QED is effective for both RTL and high-level synthesis (HLS) design flows, it integrates seamlessly with HLS flows. Our A-QED results on several hardware accelerator designs demonstrate its practicality and effectiveness: 1. A-QED detected all bugs detected by conventional verification flow. 2. A-QED detected bugs that escaped conventional verification flow. 3. A-QED improved verification productivity dramatically, by 30X, in one of our case studies (1 person-day using A-QED vs. 30 person-days using conventional verification flow). 4. A-QED produced short counterexamples for easy debug (37X shorter on average vs. conventional verification flow).

Eshan Singh

Papers

Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs

A structured approach to post-silicon validation and debug using symbolic quick error detection

Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking

Logic Bug Detection and Localization Using Symbolic Quick Error Detection

A-QED Verification of Hardware Accelerators