The use of a laser to inject faults into SRAM memory cells is well known. However, the corresponding fault model is often unknown or misunderstood: the induced faults may be described as bit-flip or bit-set/reset faults. We have investigated in this paper whether the bit-set/reset fault model or bit-flip fault model may be encountered in SRAMs. First, the fault model of a standalone SRAM was considered. Experiments revealed that the relevant fault model was the bit-set/reset. This result was further investigated through electrical simulations based on the use of an electrical model of MOS transistors under laser illumination. Then, fault injections have been performed on the RAM memory of a micro-controller to check the validity of the previous results based on experiments and simulations.

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Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells

This paper presents a new methodology based upon backside laser irradiations to characterize the sensitivity of power devices towards Single-Event Burnout. It is shown that this technique can be used to define the safe operating area

Characterization of Single-Event Burnout in Power MOSFET Using Backside Laser Testing

Device simulations of laser induced SEU in an SRAM cell are performed with pulse durations from 100 fs to 100 mus. SEU threshold energy is notably dependent on the pulse duration. Two regimes are identified and modeled analytically and electrically.

Influence of Laser Pulse Duration in Single Event Upset Testing

This work presents new results to compare EADS CCR laser experiments and heavy ion tests. More precisely, this study describes the influence of the laser spot size on the threshold energy of the SEU cross-section curves. A new methodology is proposed to correlate laser to heavy ion results.

Effects of beam spot size on the correlation between laser and heavy ion SEU testing

The laser energy thresholds for SEU for SOI 1-Mbit SRAMs built in Sandia's 0.35-μm SOI technology were measured using carrier generation by two-photon absorption. The laser measurements were correlated to heavy-ion threshold LET measurements to determine an empirical relationship between laser energy threshold and heavy-ion threshold LET. This empirical relationship was used to estimate the threshold LETs for other circuits built in Sandia's 0.35-μm SOI technology and SRAMs built in IBM's 45 and 65-nm SOI technologies. For an ASIC built in Sandia's 0.35-μm SOI technology the estimated threshold from laser measurements was close to the measured heavy-ion threshold LET. However, for a dual-port SRAM also built in Sandia's 0.35-μm SOI technology and for the 45- and 65-nm IBM SOI SRAMs, the threshold LETs estimated from laser measurements did not correlate to the measured heavy-ion threshold LETs. For the IBM SRAMs, the likely cause of the discrepancy between the threshold LETs estimated from laser measurements and the threshold LETs measured by heavy-ion testing is due to the laser pulse simultaneously injecting charge into multiple transistors within a memory cell and/or in adjacent memory cells. This is due to the relatively large size of the laser spot size compared to the size of the SEU sensitive volume of the IBM SOI devices. The hardness assurance implications of these results are discussed.

Estimation of Heavy-Ion LET Thresholds in Advanced SOI IC Technologies From Two-Photon Absorption Laser Measurements

This paper presents a new methodology for single-event upset laser testing of commercial off-the-shelf SRAMs. This methodology is based on backside laser test and is illustrated with some experimental results obtained with a new dedicated laser test bench.

F. Mounsi

Papers

Backside SEU laser testing for commercial off-the-shelf SRAMs

Life margin assessment with Physics of Failure Tools application to BGA packages