Showing papers in "Microelectronics Reliability in 2006"

TL;DR: An overview of the evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented and a physical model is proposed which could be used to more accurately predict the transistor degradation.

TL;DR: Negative bias temperature instability (NBTI) as discussed by the authors is a critical reliability phenomenon in advanced CMOS technology, in which interface traps and positive oxide charge are generated in metaloxide-silicon (MOS) structures under negative gate bias, in particular at elevated temperature.

TL;DR: An algorithm of the intuitionistic fuzzy fault-tree analysis is proposed in this paper to calculate fault interval of system components and to find the most critical system component for the managerial decision-making based on some basic definitions.

TL;DR: The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO2 barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakageCurrent due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.

TL;DR: Results indicate that solder joints with a low Ag weight content and substrate pads with OSP coating both enhance the drop resistance of the board-level test vehicle.

TL;DR: Drop impact solder joint reliability for plastic ball grid array, very-thin quad flat no-lead (VQFN) and plastic quad flat pack (PQFP) packages was investigated and the VQFN package is the most resistant to drop impact failures due to its small size and weight.

TL;DR: The intrinsic failure mechanisms and reliability models of state-of-the-art MOSFETs are reviewed and a new approach for accurately predicting circuit reliability and failure rate from the system point of view is proposed.

TL;DR: In this article, gate current in metaloxide-semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied, along with the particularities of tunneling in modern MOS transistors, including direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling.

TL;DR: Both thin surface layers of CoWP or Ta/TaN and the addition of Ti in the Cu lines significantly reduced the Cu/cap interface diffusivity and remarkably improved the electromigration lifetime when compared with Cu lines capped with SiN x or SiC x N y H z .

TL;DR: The main factors that could increase the lifetime expectancy of power modules in such harsh environments will be identified.

TL;DR: Based on the on-state voltage drop monitoring at high current, an alternative method for thermo-sensitive parameters calibration is reported that allows the simultaneous calibration of the series resistance and power devices voltage drop on temperature.

TL;DR: Reliabilities of joints for power semiconductor devices using a Bi-based high temperature solder, prepared by mixing of the CuAlMn particles and molten Bi to overcome the brittleness of Bi, has been studied.

TL;DR: The results show that for small, random voids, the thermal resistance, θjc, increases linearly with void volume percentage, V%, according to the equation θJC = 0.007V + 1.4987, and for large, contiguous voids the increase follows the exponential relationship,θjc =–1.427e0.015V.

TL;DR: Equations of motion of the board-level test vehicle are derived based on coordinate transformations that translate the input acceleration pulse into the effective support excitation load on the test vehicle, which provides computationally economical solutions.

TL;DR: This paper presents constitutive and reliability information on one of the widely used high lead solder materials as a baseline, and discusses potential alternative technologies for high temperature solders with the goal of identifying a cost-effective lead-free solder that can be used at temperatures greater than 200 °C.

TL;DR: No intermetallics formation or other microstructural change have been found on these interfaces up to 120 days at 150 °C, which was related to the full solubility of the materials along these interfaces, suggesting that they can be a successful industrial solution for the next generation of packages.

TL;DR: The paper describes the physics of the signal generation, provides the experimental setup, and discusses the accuracy and the suitability of the technique under operating conditions of the devices.

TL;DR: Commercial-off-the-shelf COTS area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions.

TL;DR: In this paper, ordinary FMEA (Failure Mode and Effects Analysis) was applied during the design phase of an electric motor control system for vehicle HVAC (Heating/Ventilation/Air Conditioning) and proved to be inadequate.

TL;DR: The main purpose of this study is to determine the effective heat pipe thermal conductivity in transient state during start up the pipe operation and temperature increase.

TL;DR: The support excitation scheme incorporated with the implicit time integration scheme is implemented to study transient structural responses of a board-level chip-scale package subjected to consecutive drops and accumulated stresses, plastic strains, and plastic strain energy densities on the solder joints under repetitive drop impacts are investigated.

TL;DR: Three conditions with two ramp rates and two temperature ranges were applied to resistor 2512 and PBGA 256 test vehicles assembled with SnPb and Pb-free solders, showing that the higher ramp rate reduced the testing time while retaining the same failure modes, and that the damage per cycle increased with the temperature difference.

TL;DR: The investigation shows that the initial stage of ECM is also the rate controlling stage and resistance decrease paths may be established prior to the appearance of dendritic migration paths.

TL;DR: This paper presents an analysis of the use of red phosphorus as a flame retardant material in encapsulated microcircuits and discusses the reliability risks and chemical reactions that can arise when red phosphorus is exposed to ambient humidity to form highly mobile ions and oxygen-containing phosphorus acids.

TL;DR: An intelligent online temperature compensation scheme using ANN technique has been described and leads to an error reduction of approximately 98% from temperature uncompensated value.

TL;DR: A probabilistic model is applied to describe the phenomenon of whiskers growth in terms of whisker density, length and growth rate and the results of an experimental tin whisker growth study of bright tin on brass substrates are presented.

TL;DR: Investigating the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL) finds effects of current polarity and crowding are key factors to observed electromigration behavior of flip- chip packages.

TL;DR: This experiment demonstrated the importance of Cu in the TDDB behaviour of low-k dielectrics, but also demonstrated that the presence of Cu was not a necessary condition for failure and the behaviour at low fields near use conditions may have little relationship to the predictions obtained from the results of typical TDDB testing.

TL;DR: The finite element analysis is performed to investigate characteristics of current crowding in a flip-chip solder bump subjected to a constant applied current and it is found that under such a condition,Current crowding is induced solely by the structural geometry of the system.

TL;DR: It was observed that low hydrogen content in the films is in good correlation with electrical quality and kinetic of the charging/discharging processes, which can explain the charging behaviour.