Showing papers by "Fabrizio Lombardi published in 1993"

Detection of defective media in disks

Abstract: The authors present new improved methods for detecting latent sector faults in a disk subsystem as caused by media deterioration of the disk magnetic storage material. Usually, sectors in a disk are accessed using uneven patterns causing some of the sectors to be accessed only seldom. In case of media deterioration on the rarely accessed sectors, a latent disk fault may remain undetected for a long time. To detect latent sector faults, a disk is scanned through periodically. An adaptive algorithm is proposed to utilize the idle time for the disk for scanning commonly used disks that comply with SCSI-II interface standards.

On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements

Abstract: The reconfiguration of multipipeline arrays in the presence of both faulty processing elements (PEs) and switching elements (SEs) is addressed. Different fault models are used for the PEs and SEs: a PE can be either fault free or faulty; a SE is modeled using a novel functional approach which relates its switching capabilities to its status. This permits a PE to retain a partial functionality in the presence of a fault. An appropriate transformation of the multipipeline array reconfiguration problem to a maximum flow problem is then presented. The conditions under which this transformation is possible, are fully analyzed. A reconfiguration algorithm based on the maximum flow algorithm is presented; the proposed algorithm is optimal as the number of reconfigured pipelines is maximized. >

An Adaptive System-Level Diagnosis Approach for Mesh Connected Multiprocessors

Abstract: Traditional adaptive centralized system diagnosis assumes a fully connected network topology, hence it can not be used in a number of classes of multiprocessor systems, such as meshes. This paper proposes an adaptive system-level diagnosis algorithm for meshes with wraparound, such as Intel Paragon machine. It is proved that the diagnosis cost required by the proposed approach is lower than the known diagnosis algorithms which can be applied to mesh architectures. Also over-d fault problem can be efficiently solved by our method, where d is the diagnosability.

On the testability of array structures for FFT computation

Abstract: This article presents new approaches for testing VLSI array architectures used in the computation of the complexN-point Fast Fourier Transform Initially, an unrestricted single cell-level fault model is considered The first proposed approach is based on a process whose complexity is independent (or C- as constant) of the number of cells in the FFT architecture This is accomplished by showing a topological equivalence between the FFT array and a linear (one-dimensional) array The process of fault location is also analyzed The second proposed method is based on a testing process whose complexity is linear with respect to the number of stages (columns) of the FFT array A component-level fault model is also proposed and analyzed The implications of this model on the C-testability process are fully described

On the reconfigurable operation of arrays with defects for image processing

Abstract: The authors examine the operation and a reconfiguration strategy for two-dimensional SIMD parallel architectures in the presence of manufacturing cluster defects and/or link defects when used for image processing. The proposed technique is based on a conceptual reconfiguration of processing elements by covering each large defect area with a set of fault-free elements, thus creating a loss of image resolution instead of a loss of image data. The proposed technique has been emulated on a 2048 PE MasPar architecture assuming both mesh connected elements (four-way connection) and eight-way connections.

Emulating Reconfigurable Arrays for Image Processing Using the MasPar Architecture

Abstract: This paper examines a fault tolerant scheme for two-dimensional arrays of processors which functionally reconfigures the array without the use of spares. Reconfiguration approaches for different interconnection networks are analyzed. Also, three approaches are proposed for mapping image data to and from the array, depending on the type of array and computational power available in each processing element. The proposed reconfiguration approaches have been emulated on a 32x64 processor MasPar array computer.

Testing constant-geometry FFT arrays for wafer scale integration

Abstract: Two approaches for testing constant-geometry wafer scale integration (WSI) array architectures used in the computation of the complex N-point fast Fourier transform (FFT) under a single combinational fault model are presented. Initially, an unrestricted single cell-level fault model is considered. The first approach is based on a process whose complexity is independent of the number of cells in the FFT architecture. The second method is based on a testing process whose complexity is linear with respect to the number of stages (columns) of the FFT array. No additional hardware is required in this case. A component-level fault model is also proposed and analyzed. >

An approach for reducing the programming cost of soft switches in reconfigurable WSI arrays

Abstract: Discusses the cost involved in the programming of nonpermanent (soft) switching elements in an augmented interconnection network for reconfigurable two-dimensional wafer scale integration (WSI) arrays. The formulation and characterization of two different figures for evaluating the cost of switch programming are given. A new cost, referred to as the adjusted cost, is introduced for establishing a relationship between the programming process and the switching modes of the target array. Reduction in cost is achieved by two techniques: redundancy reduction given by the number of times a switch is programmed in a tree; and a relaxation technique, referred to as compression, in which each of the two cost figures is primarily considered for reduction. >

An adaptive system-level diagnosis approach for hypercube multiprocessors

Abstract: This paper proposes a hierarchical adaptive system-level diagnosis approach for hypercube systems. Three measures for diagnosis cost (diagnosis time, number of tests and number of test links) are analyzed for the proposed algorithm. It is proved that the diagnosis cost required by this algorithm is lower than in the previous diagnosis algorithms in most of the fault cases. It is shown that the diagnosis cost for the proposed algorithm depends on the number of faulty units in the system and the cost is extremely low when only a small number of faulty units exist. It is shown that this algorithm is even characterized by lower costs than a pessimistic diagnosis algorithm which trades lower diagnosis cost for a lower degree of accuracy. >

GID-testable two-dimensional sequential arrays for self-testing

Abstract: This paper presents an approach for easily testable two-dimensional sequential arrays. This approach is an extension of GID (Group Identical and Different)-testability of combinational arrays in our previous work. In a GID-testable two-dimensional array, the primary x and y outputs are organized into groups and every group has more than one output. GID-testability not only ensures that identical test responses can be obtained from every output in the same group when the array is fault free, but it also ensures at least one output has different test responses from other outputs in a group when a cell in the array is faulty. Therefore, all faults can be detected under the assumption of a single faulty cell model. It is proved that an arbitrary two-dimensional sequential array is GID-testable if seven x-states and seven y-states are added to the original flow table of the basic cell of the array. >

On the design for testability of sequential circuits

Abstract: Presents a new approach for design-for-testability (DFT) of sequential circuits. The proposed approach is based on augmenting the system under test (SUT) with additional circuitry such that the combinational part of the SUT and the sequential part (i.e. the flip-flops) can be tested independently (disjoint testing). >

On the minimal test set for single fault location

Abstract: A new heuristic algorithm (based on the fault dictionary approach) that finds the minimal test set for locating single faults (of the stuck-at type) in a digital circuit, thus reducing the size of the fault dictionary, is presented. The proposed algorithm is based on finding the transitive closure of the vectors in the test set with respect to the functional dominancies using Warshall's algorithm for binary matrices. The space complexity of the proposed algorithm is O(ma. >

On the testability of FFT arrays

Abstract: This paper presents new approaches for testing VLSI array architectures used in the computation of the complex N-point fast Fourier transform. Initially, an unrestricted single cell-level fault model is considered. The first proposed approach is based on a process whose complexity is independent (or C- as constant) of the number of cells in the FFT architecture. This is accomplished by showing a topological equivalence between the FFT array and a linear (one-dimensional) array. The process of fault location is also analyzed. The second proposed method is based on a testing process whose complexity is linear with respect to the number of stages (columns) of the FFT array. A component-level fault model is also proposed and analyzed. The implications of this model on the C-testability process are fully described. >