FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<<ETX>>

Extraction and Simulation of Realistic CMOS Faults using

This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test,...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.

On-Line Testing for VLSI—A Compendium of Approaches

In this paper we propose a structure dependent method for the systematic design of a self-checking circuit which is well adapted to the fault model of single gate faults and which can be used in test mode.

/pdf/self-checking-combinational-circuits-with-unidirectionally-3hrb8c7g8c.pdf

Self-Checking Combinational Circuits with Unidirectionally Independent Outputs

In this paper, a new method for the design of unidirectional combinational circuits is proposed Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters Unlike previous methods, it is not necessary to localize all the inverters of the circuit at the primary inputs The average area over head for the described method of circuit transformation is 16% of the original circuit, which is less than half of the area overhead of other known methods The transformed circuits are monitored by Berger codes, or by the least significant two bits of a Berger code All single stuck-at faults are detected by the method proposed

A New Design Method for Self-Checking Unidirectional Combinational Circuits

We present new properties of summation codes which are used for organizing functional control circuits for discrete systems.

On summation code properties in functional control circuits

This article presents novel input and output encoding techniques such that the resulting circuit is bidirectional error-free. The circuit can be fully optimized and any types of gates can be used. These schemes are used to design the functional part of a self-checking circuit. The input encoding algorithm can be applied to any circuit without significantly increasing the input lines. The output encoding technique involves graph-embedding which is done with heuristic method of polynomial complexity. The heuristic technique produces nearly optimal output encoding. Previously published work restrict the types of gates used in the circuit to non-inversion gates (AND/OR), and use inverters only at the inputs. The proposed techniques have a clear advantage over the currently available techniques because they allow the use of any types of gates. These techniques do not necessarily increase the overhead when applied to different MCNC benchmark circuits as the experimental results indicate. The only restriction is that either the inputs or the outputs have to be symbolic, and the two-level description of a circuit has to be given.

Self-checking combinational circuit design for single and unidirectional multibit error

A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary
MOS) designs for multiple faults is presented in this paper. The existing techniques for
self checking design consider only single faults, and suffer from high silicon area
overhead. The multiple faults considered in this paper are multiple breaks, multiple
transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design,
small modifications (addition of two-weak transistors) make the original circuit totally
self-checking. Experiemntal results show the overhead, delay and power consumption
for the proposed technique. This paper also presents a technique for designing
multistage TSC FCMOS circuits.

/pdf/on-self-checking-design-of-cmos-circuits-for-multiple-faults-26ev3ja6p3.pdf

On Self-Checking Design of CMOS Circuits for Multiple Faults

A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption for the proposed technique. This paper also presents a technique for designing multistage TSC FCMOS circuits.

/pdf/on-self-checking-design-ofcmos-circuits-for-multiple-faults-462784m2im.pdf

On Self-Checking Design ofCMOS Circuits for Multiple Faults

This paper presents a technique for designing interacting finite state machines which will be totally self-checking for any single stuck-at fault. In the proposed technique m-out-of-n codes are used for both primary output and state assignments. In addition, the next state logic (NSL) for each submachine and the output logic (OL) are realized such that any single stuck-at fault results in either single bit error or unidirectional multibit error at the output. The proposed technique does not have any restriction on the way the NSL and the OL are implemented.

/pdf/an-approach-for-self-checking-realization-of-interacting-2b5u8ztkl3.pdf

An Approach for Self-Checking Realization of Interacting Finite State Machines

This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit. An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either produce single bit error or unidirectional multibit error at the output are proposed. If there are no input fault which produces bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. Thus, only single bit or unidirectional multibit error will result in the presence of a fault in the circuit. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.

/pdf/techniques-for-self-checking-combinational-logic-synthesis-1myc744w8e.pdf

Fadi Busaba

Papers

Self-checking combinational circuit design for single and unidirectional multibit error

On Self-Checking Design of CMOS Circuits for Multiple Faults

On Self-Checking Design ofCMOS Circuits for Multiple Faults

An Approach for Self-Checking Realization of Interacting Finite State Machines

Techniques for Self-Checking Combinational Logic Synthesis