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Fakhreddine Ghaffari

Researcher at Cergy-Pontoise University

Publications -  60
Citations -  495

Fakhreddine Ghaffari is an academic researcher from Cergy-Pontoise University. The author has contributed to research in topics: Decoding methods & Low-density parity-check code. The author has an hindex of 10, co-authored 56 publications receiving 373 citations. Previous affiliations of Fakhreddine Ghaffari include Centre national de la recherche scientifique & École nationale supérieure de l'électronique et de ses applications.

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Journal ArticleDOI

An embedded implementation based on adaptive filter bank for brain–computer interface systems

TL;DR: Performing dynamic filtering of EEG-signals using WOLA increases the recognition rate of ERD/ERS patterns of motor imagery brain activity and reduces the overall classification error rate for the three datasets of the BCI-competition.
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Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

TL;DR: This paper introduces a new approach to cost-effective, high-throughput hardware designs for low-density parity-check (LDPC) decoders, called nonsurjective finite alphabet iterative decmoders (NS-FAIDs), which exploits the robustness of message-passing LDPC decoder to inaccuracies in the calculation of exchanged messages.
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A Hardware/Software Prototype of EEG-based BCI System for Home Device Control

TL;DR: It is shown that the proposed architecture can effectively extract discriminative features for motor imagery with a maximum frequency of 150 MHz, and was validated on EEG data of twelve subjects from the BCI competition data sets.
Proceedings ArticleDOI

FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding

TL;DR: Two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding are proposed: the Partially OMS, which performs only partially the offset correction, and the Imprecise Partially EMM decoding, which introduces a further level of impreciseness in the check-node processing unit.
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Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping

TL;DR: An efficient hardware architecture which minimizes the resource overhead needed to implement the random perturbations of the PGDBF is proposed, providing a competitive hard-decision LDPC decoding solution for current standards.