Exponential bandwidth scaling has been a fundamental driver of the growth and popularity of the Internet. However, increases in bandwidth have been accompanied by increases in power consumption, and despite sustained system design efforts to address power demand, significant technological challenges remain that threaten to slow future bandwidth growth. In this paper we describe the power and associated heat management challenges in today's routers. We advocate a broad approach to addressing this problem that includes making power-awareness a primary objective in the design and configuration of networks, and in the design and implementation of network protocols. We support our arguments by providing a case study of power demands of two standard router platforms that enables us to create a generic model for router power consumption. We apply this model in a set of target network configurations and use mixed integer optimization techniques to investigate power consumption, performance and robustness in static network design and in dynamic routing. Our results indicate the potential for significant power savings in operational networks by including power-awareness.

/pdf/power-awareness-in-network-design-and-routing-17zkt9k3ta.pdf

Power Awareness in Network Design and Routing

At some point in the future, how far out we do not exactly know, wireless access to the Internet will outstrip all other forms of access bringing the freedom of mobility to the way we access the we...

ACM SIGCOMM computer communication review

A system, method, and computer program product are provided for a memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.

System, method, and computer program product for improving memory systems

This paper discusses the architecture and performance studies of Datacenter Optical Switch (DOS) designed for scalable and high-throughput interconnections within a data center. DOS exploits wavelength routing characteristics of a switch fabric based on an Arrayed Waveguide Grating Router (AWGR) that allows contention resolution in the wavelength domain. Simulation results indicate that DOS exhibits lower latency and higher throughput even at high input loads compared with electronic switches or previously proposed optical switch architectures such as OSMOSIS [4, 5] and Data Vortex [6, 7]. Such characteristics, together with very high port count on a single switch fabric make DOS attractive for data center applications where the traffic patterns are known to be bursty with high temporary peaks [13]. DOS exploits the unique characteristics of the AWGR fabric to reduce the delay and complexity of arbitration. We present a detailed analysis of DOS using a cycle-accurate network simulator. The results show that the latency of DOS is almost independent of the number of input ports and does not saturate even at very high (approx 90%) input load. Furthermore, we show that even with 2 to 4 wavelengths, the performance of DOS is significantly better than an electrical switch network based on state-of-the-art flattened butterfly topology.

DOS: a scalable optical switch for datacenters

This paper examines the role of optical and electronic technologies in future high-capacity routers. In particular, optical and electronic technologies for use in the key router functions of buffering and switching are compared. The comparison is based on aggressive but plausible estimates of buffer and switch performance projected out to around 2020. The analysis of buffer technologies uses a new model of power dissipation in optical-delay-line buffers using optical fiber and planar waveguides, including slow-light waveguides. Using this model together with models of storage capacity in ideal and nonideal slow-light delay lines, the power dissipation and scaling characteristics of optical and electronic buffers are compared. The author concludes that planar integrated optical buffers occupy larger chip area than electronic buffers, dissipate more power than electronic buffers, and are limited in capacity to, at most, a few IP packets. Optical fiber-based buffers have lower power dissipation but are bulky. The author also concludes that electronic buffering will remain the technology of choice in future high-capacity routers. The power dissipation of high-capacity optical and electronic cross connects for a number of cross connect architectures is compared. The author shows that optical and electronic cross connects dissipate similar power and require a similar chip area. Optical technologies show a potential for inclusion in high-capacity routers, especially as the basis for arrayed-waveguide-grating-based cross connects and as components in E/O/E interconnects. A major challenge in large cross connects, both optical and electronic, will be to efficiently manage the very large number of interconnects between chips and boards. The general conclusion is that electronic technologies are likely to remain as integral components in the signal transmission path of future high-capacity routers. There does not appear to be a compelling case for replacing electronic routers with optically transparent optical packet switches

The Role of Optics and Electronics in High-Capacity Routers

FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DCs) and are used to offload and accelerate specific services, but they are not yet available to cloud users. This puts the cloud deployment of compute-intensive workloads at a disadvantage compared with on-site infrastructure installations, where the performance and energy efficiency of FPGAs are increasingly being exploited for application-specific accelerators and heterogeneous computing. The cloud is housed in DCs, and DCs are based on ever shrinking servers. Today, we observe the emergence of hyper scale data centers, which are based on densely packaged servers. The shrinking form factor brings the potential to deploy FPGAs on a large scale in such DCs. These FPGAs must be deployed as independent DC resources, and they must be accessible to the cloud users. Therefore, we propose to change the traditional paradigm of the CPU-FPGA interface by decoupling the FPGA from the CPU and connecting the FPGA as a standalone resource to the DC network. This allows cloud vendors to offer an FPGA to users in a similar way as a standard server. As existing infrastructure-as-a-service (IaaS) mechanisms are not suitable, we propose a new Open Stack (open source cloud computing software) service to integrate FPGAs in the cloud. This proposal is complemented by a framework that enables cloud users to combine multiple FPGAs into a programmable fabric. The proposed architecture and framework address the scalability problem that makes it difficult to provision large numbers of FPGAs. Together, they offer a novel solution for processing large and heterogeneous data sets in the cloud.

Enabling FPGAs in Hyperscale Data Centers

Addressing the ever growing capacity demand for packet switches, current research focuses on scheduling algorithms or buffer bandwidth reductions. Although these topics remain relevant, our position is that the primary design focus for systems beyond 1 Tb/s must be shifted to aspects resulting from packaging disruptions. Based on trends such as increased link rates and improved CMOS technologies, we derive new design factors for such switch fabrics. For instance, we argue that the packet round-trip transmission time within the fabric has become a major design parameter. Furthermore, we observe that high-speed fabrics have become extremely dependent on serial I/O technology that is both high speed and high density. Finally, we conclude that in developing the architecture, packaging constraints must be put first and not as an afterthought, which also applies to solving the tremendous power consumption challenges.

/pdf/current-issues-in-packet-switch-design-wy09p1kie2.pdf

Current issues in packet switch design

This 4-TBPS packet switch uses a combined input- and crosspoint-queued (CICQ) structure with virtual output queuing at the ingress to achieve the scalability of input-buffered switches, the performance of output-buffered switches, and low latency.

A four-terabit packet switch supporting long round-trip times

According to embodiments of the invention, there is provided a method for operating a network processor. The network processor receiving a first data packet in a stream of data packets and a set of receive-queues adapted to store receive data packets. The network processor processing the first data packet by reading a flow identification in the first data packet; determining a quality of service for the first data packet; mapping the flow identification and the quality of service into an index for selecting a first receive-queue for routing the first data packet; and utilizing the index to route the first data packet to the first receive-queue.

Selection of receive-queue based on packet attributes

FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DC). They are used as accelerators to boost the compute power of individual server nodes and to improve the overall power efficiency. However, this approach limits the number of FPGAs per node and hinders the acceleration of large-scale distributed applications.

Francois Abel

Papers

Enabling FPGAs in Hyperscale Data Centers

Current issues in packet switch design

A four-terabit packet switch supporting long round-trip times

Selection of receive-queue based on packet attributes

Network-attached FPGAs for data center applications