A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-voltage (0.5 V) and low-power (4.535 mW) monolithic biomedical system-on-a-chip (SOC) consisting of a receiver, a transmitter, a microcontrol unit, and an analog-to-digital converter (ADC), implemented in a 0.18-μm CMOS technology for intrabody communication is first reported. The SOC can take command through a human body and activate (or turn on) the ADC and transmitter inside the SOC. Then, a biomedical signal is converted to digital format and transmitted to the RF gateway through a human body. With this transmission methodology and the proposed SOC circuit, it is much more power efficient than wireless communication. Moreover, since no antenna is required, the chip size of the SOC is only 1.5 mm2, excluding the test pads.

A 0.5-V Biomedical System-on-a-Chip for Intrabody Communication System

This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-/spl mu/m CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point.

Low-voltage 1.9-GHz front-end receiver in 0.5-/spl mu/m CMOS technology

This paper presents an inductive power transmission coil for biosensor-based telemetric implants. Using stacked spirals reduces the consumed space and the self-resonant frequency (SRF) of the spiral and the required power transmission frequency for the implanted device. A four-layer 15 mm × 15 mm spiral coil of seven turns is simulated in CST Microwave Studio (TM), constructed and tested in hardware with comparable results. Measurements also include the receipt of power inductively from an energized array of spirals powered by a Class-E transmitter at 27 MHz, and rectified to 1 V for biosensor applications.

Stacked Spirals for Biosensor Telemetry

We report an integrated RF circuit topology that can be used to realize low voltage (i.e., 1 V) RF integrated circuits. The scheme uses on-chip capacitively coupled resonating elements to DC isolate circuit elements that under the present art are connected in series and share a common DC current. The topology is applied to several commonly used RF integrated circuit topologies (i.e., low-noise amplifiers and mixers). A comparison is made between a low-voltage version of a cascode amplifier and the classic cascode amplifier. The low-voltage version (i.e., 1 V) is shown to have a similar distortion specification as the classic 2 V low-noise cascode amplifier. The low-voltage version has a 0.22 dB improvement in noise figure.

G. Beck

Papers

A low-voltage design technique for RF integrated circuits