Showing papers in "IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing in 1998"

Low-IF topologies for high-performance analog front ends of fully integrated receivers

Abstract: When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

Designing 1-V op amps using standard digital CMOS technology

Abstract: This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 /spl mu/W, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57/spl deg/ phase margin for a 22-pF load capacitance.

CMOS transconductance multipliers: a tutorial

Abstract: Real time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been available for some time, the CMOS multiplier implementation is still a challenging subject especially for low-voltage and low-power circuit design. Despite the large number of papers proposing new CMOS multiplier structures, they can be roughly grouped into a few categories. This tutorial provides a complete survey of CMOS multipliers, presents a unified generation of multiplier architectures, and proposes the most recommended MOS multiplier structure. This tutorial could serve as a starting reference point (and metric) for comparison of new CMOS multiplier circuit configurations. An illustrative CMOS chip prototype verifying theoretical results is presented.

A tutorial introduction to research on analog and mixed-signal circuit testing

Abstract: Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

Multiresolution watermarking for digital images

Abstract: In this paper, a multiresolution-based technique for embedding digital "watermarks" into images is proposed. The watermarking technique has been proposed as a method by hiding secret information in the images so as to discourage unauthorized copying or attesting the origin of the images. In our method, we take advantage of multiresolution signal decomposition. Both the watermark and the host image are composed of multiresolution representations with different structures and then the decomposed watermarks of different resolution are embedded into the corresponding resolution of the decomposed images. In case of image quality degradation, the low-resolution rendition of the watermark will still be preserved within the corresponding low-resolution components of the image. The experimental results show that the proposed watermarking technique results in an almost invisible difference between the watermarked image and the original image, and is robust to common image processing operations and JPEG lossy compression.

Repeater design to reduce delay and power in resistive interconnect

Abstract: In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current, In order to develop a repeater design methodology, a timing model characterizing a complementary metal-oxide-semiconductor (CMOS) inverter driving a resistance-capacitance (RC) load is presented. The model is based on the Sakurai short-channel /spl alpha/-power law model of transistor operation. The inverter model is applied to the problem of repeaters to produce design expressions for determining the optimum number of uniformly sized repeaters to be inserted along a resistive interconnect line for reduced delay. For a wide variety of typical RC loads, this analytical repeater model exhibits a maximum error of 16% as compared to a dynamic circuit simulator (SPICE). The advantage of uniformly sized repeaters versus tapered-buffer repeaters is also investigated using the repeater model presented in this paper. It is shown that uniform repeaters remain advantageous over tapered buffers and tapered-buffer repeaters even with relatively small resistive RC loads. An expression for the short-circuit power dissipation of a repeater driving an RC load is presented, A comparison of the short-circuit power dissipation to the dynamic power dissipation in repeater chains and related power/delay tradeoffs are made.

Fixed-point optimization utility for C and C++ based digital signal processing programs

Abstract: Fixed-point optimization utility software is developed that can aid scaling and wordlength determination of digital signal processing algorithms written in C or C++. This utility consists of two programs: the range estimator and the fixed-point simulator. The former estimates the ranges of floating-point variables for purposes of automatic scaling, and the latter translates floating-point programs into fixed-point equivalents to evaluate the fixed-point performance by simulation. By exploiting the operator overloading characteristics of C++, the range estimation and the fixed-point simulation can be conducted by simply modifying the variable declaration of the original program. This utility is easily applicable to nearly all types of digital signal processing programs including nonlinear, time-varying, multirate, and multidimensional signal processing algorithms. In addition, this software can be used to compare the fixed-point characteristics of different implementation architectures. An optimization example for an 8/spl times/8 inverse discrete cosine transform (IDCT) architecture that conforms to the IEEE standard specifications is presented. The optimized results require 8% fewer gates when compared with the previous best implementation.

Optimized frequency-shaping circuit topologies for LDOs

Abstract: Typical low drop-out (LDO) regulator architectures suffer from an inherent load regulation performance limitation. This limitation manifests itself through limited DC open-loop gain, and results from stringent closed-loop bandwidth requirements. The frequency response of the system is highly sensitive to the loading conditions, thereby making proper compensation a laborious endeavor. This paper discusses and addresses the limitation on regulating performance imposed by frequency compensation. Several LDO circuit topologies are subsequently developed to this end. They enhance load regulation performance by relaxing the DC open-loop gain restrictions. The circuit structures essentially alter the frequency response of the system via the error amplifier. A low drop-out regulator adopting an embodiment of the proposed technique was fabricated in the MOSIS 2-/spl mu/m process technology. The system, designed for an output capacitor of 4.7 /spl mu/F, was stable with an equivalent series resistance (ESR) ranging from 0 to 12 /spl Omega/, bypass capacitors ranging from 0 to 2.2 /spl mu/F, and a load current ranging from 0 to 50 mA.

Periodically nonuniform sampling of bandpass signals

Abstract: It is known that a continuous time signal x(i) with Fourier transform X(/spl nu/) band-limited to |/spl nu/|

On the design of constant settling time AGC circuits

Abstract: The generalized design of Automatic Gain Control (AGC) circuits that have constant settling time is described. Each of the major components of the AGC circuit is modeled and the criteria to obtain a gain settling time independent of the absolute gain are determined. The method developed works with arbitrary monotonic nonlinear functions in the gain control characteristic of the variable gain amplifier. Several AGC circuits are simulated at the behavioral level to show the benefits of the technique developed.

Optimal parameters for /spl Delta//spl Sigma/ modulator topologies

Abstract: A systematic study of single-loop, cascaded, and multibit /spl Delta//spl Sigma/ modulators of second to fourth order is presented, based on a combination of behavioral simulations and linear modeling. Constraints for optimal performance and precise guidelines for the choice of parameters are derived. Moreover, the optimal parameters and the corresponding performance are found and given in tables. A graph showing the maximal achievable performance of each topology as a function of the oversampling ratio is presented, offering a valuable help for the design of analog-to-digital converters.

Spectrum folding and phase noise in LC tuned oscillators

Abstract: We present a theory of the noise transfer in LC tuned oscillators accounting for the nonlinear operation of the transconductor. We show that the transconductor switching causes a folding of the wide-band noise such as the thermal noise of the spreading resistance of the bipolar transistors and the noise of the tail current generator. The effect is similar to what happens in sampled systems, however, for a careful evaluation of the oscillator phase noise, the correlations between the folded terms is of chief importance. We show how to account for the effect, we assess the impact on the oscillator noise performance and we give the guidelines for the circuit optimization.

A new current-controlled multiphase sinusoidal oscillator using translinear current conveyors

Abstract: A multiphase sinusoidal oscillator circuit is presented. The oscillator can produce N output-currents (N being even or odd) equally spaced in phase. The circuit uses translinear bipolar second-generation current-controlled conveyors, grounded capacitors and enjoys low active and passive sensitivities and independent current-control of the frequency of oscillation.

A generalized sampling theory without band-limiting constraints

Abstract: We consider the problem of the reconstruction of a continuous-time function f(x)/spl isin/H from the samples of the responses of m linear shift-invariant systems sampled at 1/m the reconstruction rate. We extend Papoulis' generalized sampling theory in two important respects. First, our class of admissible input signals (typ. H=L/sub 2/) is considerably larger than the subspace of band-limited functions. Second, we use a more general specification of the reconstruction subspace V(/spl psi/), so that the output of the system can take the form of a band-limited function, a spline, or a wavelet expansion. Since we have enlarged the class of admissible input functions, we have to give up Shannon and Papoulis' principle of an exact reconstruction. Instead, we seek an approximation f/spl isin/V(/spl psi/) that is consistent in the sense that it produces exactly the same measurements as the input of the system. This leads to a generalization of Papoulis' sampling theorem and a practical reconstruction algorithm that takes the form of a multivariate filter. In particular, we show that the corresponding system acts as a projector from H onto V(/spl psi/). We then propose two complementary polyphase and modulation domain interpretations of our solution. The polyphase representation leads to a simple understanding of our reconstruction algorithm in terms of a perfect reconstruction filter bank. The modulation analysis, on the other hand, is useful in providing the connection with Papoulis' earlier results for the band-limited case. Finally, we illustrate the general applicability of our theory by presenting new examples of interlaced and derivative sampling using splines.

Multiwavelet analysis and signal processing

Abstract: In this paper we present some results and applications concerning the recent theory of multiscaling functions and multiwavelets. In particular, we present the theory in compact notation with the use of some types of recursive block matrices. This allows a flexible schematization of the construction of semi-orthogonal multiwavelets. As in the scalar case, an efficient algorithm for the computation of the coefficients of a multiwavelet transform can be obtained, in which r input sequences are involved. This is a crucial point: the choice of a good prefilter which can provide a good approximation of the true initial coefficient sequences, when applied to the input data, is critical in the context of multiwavelet analysis. We explore this problem with concrete examples, showing the strong dependence of the prefilter on the chosen multiwavelet basis. Finally, an application of the multiwavelet-based algorithm to signal compression is shown. The goal is both to compare the results obtained with different multiwavelet bases, and to test the effectiveness of multiwavelets in this kind of problem with respect to scalar wavelets.

Small side-lobe filter design for multitone data-communication applications

Abstract: An approach for realizing filter banks having improved side-lobe performance compared to approaches such as those based on inverse Fourier transforms (IFTs), especially for greater frequency differences from the passband frequencies, is presented. The approach is based on using a weighted-sum of near-adjacent IFT filters to realize the individual channel-bank filters, but with constraints added that results in significantly improved stopband performance while still achieving small reconstruction errors. The proposed channel banks are suitable for realizing multitone digital data communication systems, such as Asymmetric Digital Subscriber Line (ADSL) systems, where stopband performance is critical. Under the conditions of maximal decimation, the reconstruction is not perfect, but aliasing errors are small enough to be negligible in practical communication systems. For some cases, the filter coefficients can be determined exactly without using optimization. Given the frequency-weighting coefficients reported herein, near-optimal multirate filter banks may be designed exactly without optimization for all even n.

Discrete fractional Hartley and Fourier transforms

Abstract: This paper is concerned with the definitions of the discrete fractional Hartley transform (DFRHT) and the discrete fractional Fourier transform (DFRFT). First, the eigenvalues and eigenvectors of the discrete Fourier and Hartley transform matrices are investigated. Then, the results of the eigendecompositions of the transform matrices are used to define DFRHT and DFRFT. Also, an important relationship between DFRHT and DFRFT is described, and numerical examples are illustrated to demonstrate that the proposed DFRFT is a better approximation to the continuous fractional Fourier transform than the conventional defined DFRFT. Finally, a filtering technique in the fractional Fourier transform domain is applied to remove chirp interference.

Oversampled cosine modulated filter banks with perfect reconstruction

Abstract: Oversampled filter banks (FBs) offer more design freedom and better noise immunity than critically sampled FBs. Due to the increased computational complexity caused by oversampling, oversampled FBs allowing an efficient implementation, such as cosine modulated filter banks (CMFBs), are of particular interest. So far, only critically sampled CMFBs have been considered. In this paper, we introduce oversampled CMFBs with perfect reconstruction (PR). Extending a classification of CMFBs recently proposed by Gopinath, we consider two types of oversampled CMFBs with PR. One of these types allows linear phase filters in all channels, and comprises CMFBs recently introduced by Lin and Vaidyanathan as well as Wilson-type CMFBs. For both types of oversampled CMFBs, we formulate PR conditions in the time, frequency, and polyphase domains. It is shown that any PR CMFB corresponds to a PR DFT FB with twice the oversampling factor and that (under a specific condition) the same PR prototype can be used for both CMFB types. We also show that the frame-theoretic properties of a CMFB and of the corresponding DFT FB are closely related. In particular, it is demonstrated that the minimum-norm synthesis prototype in an oversampled PR CMFB equals that in the corresponding DFT FB. Finally, we briefly address design methods and the efficient DCT/DST-based implementation of oversampled CMFBs.

A low-voltage low-power wide-range CMOS variable gain amplifier

Abstract: In this paper, a compact low-power (LP) low-voltage (LV) metal-oxide-semiconductor-only (MOS-only) variable gain amplifier (VCA) is introduced. This amplifier based on complementary MOS (CMOS) transistors operating in strong inversion is composed of a pseudo-exponential current-to-voltage converter, analog multiplier, and output stage. The gain of the amplifier is controlled exponentially by a novel wide-range pseudo-exponential current-to-voltage converter implemented with two back-to-back connected current mirrors exhibiting superb exponential characteristic. Also, a new LV/LP composite transistor is introduced to increase the input dynamic range of the multiplier. The amplifier is fabricated using a 2-/spl mu/m MOSIS n-well process, and its simulation and measurement results are shown in detail.

Multiwavelet prefilters. 1. Orthogonal prefilters preserving approximation order p/spl les/2

Abstract: In applications using multiwavelets, there is a necessary step of associating a given discrete signal with a function in the scaling function space V/sub 0/. This association is equivalent to including a prefilter and a post-filter for the filter bank determined by the underlying multiwavelets. We give a construction for orthogonal (paraunitary) finite-impulse response (FIR) prefilters that preserve the approximation order of a given arbitrary scaling vector /spl Psi/ with approximation order p/spl les/2. We give several such prefilters for the DGHM multiwavelet.

Supply voltage scaling for temperature insensitive CMOS circuit operation

Abstract: CMOS supply voltage scaling for temperature independent gate delay is investigated. It is found that the optimum supply voltage which results in temperature insensitive operation is proportional to the threshold voltage. This voltage enables a single battery cell operation. CMOS technologies with 0.35- and 0.25-/spl mu/m size features are used as examples in this study.

A new RSA cryptosystem hardware design based on Montgomery's algorithm

Abstract: In this paper, we propose a new algorithm based on Montgomery's algorithm to calculate modular multiplication that is the core arithmetic operation in an RSA cryptosystem. The modified algorithm eliminates over large residue and has very short critical path delay that yields a very high speed processing. The new architecture based on this modified algorithm takes about 1.5n/sup 2/ clock cycles on the average to finish one n-bit RSA operation. We have implemented a 512-bit single-chip RSA processor based on the modified algorithm with Compass 0.6-/spl mu/m SPDM CMOS cell library. The simulation results show that the processor can operate up to 125 MHz and deliver the baud rate of 164 Kbits/s on the average.

A low-complexity dynamic element matching DAC for direct digital synthesis

Abstract: This paper presents and analyzes a new dynamic element matching technique for low-harmonic distortion digital-to-analog conversion The benefit of this technique over the prior art is a significantly reduced hardware complexity with no reduction in performance It is particularly appropriate for applications such as direct digital synthesis (DDS) in wireless communications systems, where low hardware complexity and low harmonic distortion are essential

Delta operator realizations of direct-form IIR filters

Abstract: The use of the delta operator in the realizations of digital filters has recently gained interest due to its good finite-word-length performance under fast sampling. We studied efficient direct form structures, and show that only some of them can be used in delta configurations, while others are evidently unstable. In this paper, we focus on the roundoff noise analysis. Of all the direct-form structures, the direct form II transposed (DFIIt) delta structure has the lowest quantization noise level at its output. This structure outperforms both the conventional direct-form (delay) structures, as well as the state-space structures for narrow-band low-pass filters with respect to output roundoff noise. Excellent roundoff noise performance is achieved at the cost of only a minor additional implementation complexity when compared with the corresponding delay realization. Complexity of a signal processor implementation of the DFIIt delta structure, which was found to be the most suitable delta structure for signal processors, is compared with those of the direct form and state-space delay structures. In addition, some hardware implementation aspects are discussed, including the minimization of the internal word length.

Residue-to-binary arithmetic converter for the moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1)

Abstract: This paper presents a new algorithm which converts moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) residue numbers to their binary equivalents; it is the first converter which has been dedicated to this particular moduli set. The complexity of conversion has been greatly reduced using new compact forms for the multiplicative inverses and the properties of modular arithmetic. A hardware implementation which utilizes adders only is also proposed. With a pipelined system, the throughput rate is that of a single (2k-1)-bit binary adder. Comparison results showed that the hardware requirements and the execution time of the new converter are less than half that needed by other converters.

A comb filter design using fractional-sample delay

Abstract: In this paper, a new comb filter design method using fractional sample delay is presented. First, the specification of the comb filter design is transformed into that of fractional delay filter design. Then, conventional finite impulse response (FIR) and allpass filter design techniques are directly applied to design fractional delay filter with transformed specification. Next, we develop a constrained fractional delay filter design approach to improve the performance of the direct design method. Finally, several design examples and an experiment of power line interference removal in an electrocardiogram (ECG) signal is demonstrated to illustrate the effectiveness of this new design approach.

Systematic design for optimization of high-speed self-calibrated pipelined A/D converters

Abstract: High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions.

A fast training algorithm for neural networks

Abstract: The recursive least squares method (RLS) is derived for the learning of multilayer feedforward neural networks. Simulation results on the XOR, 4-2-4 encoder, and function approximation problems indicate a fast learning process in comparison to the classical and momentum backpropagation (BP) algorithms.

Efficient moving-window DFT algorithms

Abstract: The authors deal with the real-valued, moving-window discrete Fourier transform. After reviewing the basic recursive versions appearing in the literature, additional recursive equations are presented. Then, these equations are combined so that nonrecursive expressions involving only consecutive discrete Fourier transform (DFT) sine components are obtained for both the DFT cosine component and squared harmonic amplitude. The computational complexity of this new scheme is finally studied and compared to that of existing methods, showing that, in most practical situations, a reduction in the operation count is achieved.

Color image processing using adaptive vector directional filters

Abstract: A new class of filters for multichannel image processing is introduced and analyzed. This class constitutes a generalization of vector directional filters. The proposed filters use fuzzy transformations of the angles among the different vectors to adapt to local data in the image. The principle behind the new filters is explained and comparisons with other popular nonlinear filters are provided. The specific case of color image processing is studied as an important example of multichannel image processing. Simulation results indicate that the new filters offer some flexbility and have excellent performance.