This paper gives an overview of the basic concepts used in the design and fabrication of gallium arsenide MESFET integrated circuits intended for gigabit logic applications. The present status of speed-power performances, packing densities, and integration levels is presented on the basis of some MSI and LSI MESFET IC realizations made possible by the principal GaAs logic approaches to date. Finally, the potential field of application and future trends of GaAs IC technology are assessed.

GaAs MESFET ICs for gigabit logic applications

A new l.s.i. oriented logic approach, low pinch-off voltage f.e.t. logic (l.p.f.l.), leading to highly versatile logic gates capable of combining high speed and low power consumption and requiring a standard fabrication process, is introduced and structures of complex logic gates realisable with this approach are described. Furthermore, a tentative comparison of the l.p.f.l. approach with other m.e.s.f.e.t. logic approaches to date is presented to show their respective design trade-offs which dictate the range of applications open to each of these approaches. The comparison is based on both computer simulations and experimental measurements on test circuits such as ring oscillators, flip-flops and binary frequency dividers.

Low pinch-off voltage f.e.t. logic (l.p.f.l.): I.s.i. oriented logic approach using quasinormally off GaAs m.e.s.f.e.t.s.

A GaAs integrated circuit has been designed and fabricated to regenerate digital data at gigabit per second rates. The circuit architecture is direct-coupled FET logic (DCFL), and the fabrication is by self-aligned etched gate on CVD epitaxial material. The circuit includes a moderate-gain input amplifier with threshold adjustment, a clocked D flip-flop for data sampling and storage, and an output buffer for driving low impedance transmission lines. Dynamic performance measurements include correct regeneration of pseudorandom data at 2.0 Gbit/s, the maximum allowed by available instrumentation, and 1010... data at 2.4 Gbit/s. Rise/fall times below 150 ps into 50 Ω were observed. A minimum gate delay of 17.8 ps and a maximum toggle frequency of 3.8 GHz were measured with associated ring oscillator and binary frequency divider circuits, respectively.

A monolithic multigigabit/second DCFL GaAs decision circuit

A review of the present status of MMIC's is given with special reference to the specific advantages and problems of monolithic microwave circuits as opposed to hybrid circuits. Some applications will also be discussed together with perspectives of future progress in the field. GaAs integrated circuits are nearly 10 years old. The first circuits were, rather surprisingly, ligic circuits. Surprisingly since the GaAs field effect transistor had already shown success with microwave analogue hybridcircuits to the extent of pushing all other devices either towards higher frequences (for Gunn and Avalanche diodes) or higher powers (for tubes) where the FET's are no longer operational. Microwave integrated circuits soon made their appearance however when Ray Pengelly prresented his first amplifier in 1976. The problem that was immediately apparent was that the surface required for microwave circuits was comparatively big for an integrated circuit although much smaller than a hybrid circuit. The real advantages of the monolithic concept, control of parasitic reactances, reproducability, reliability, were offset by the cost of the basic GaAs material since the passive elements occupied a very large proporation of the surface (> 90 %) and as a dielectric substrate GaAs is greater than 50 times more expensive than Al2 02.

Microwave Integrated Circuits on GaAs

Recent implementations of Gbs'1 integrated circuits are mentioned and used as the basis for a capability projection of the more promising technologies. After first describing the projection strategy, both the silicon and GaAs circuit families are assessed with regard to their performance limits. A shorter analysis of Josephson technology follows. For scaled down devices in silicon as well as several GaAs technologies, potential l.s.i. solutions with 2-3 GHz clock frequencies are prognosticated. The 3-6 GHz range should eventually be accessible to m.s.i. d.m.e.s.f.e.t. circuits, whereas GaAs s.d.f.l., j.f.e.t. and e.m.e.s.f.e.t. approaches promise v.l.s.i. complexity between 1 and 3 GHz. The range around 10 GHz appears to be solely a future domain of Josephson circuits (up to v.l.s.i).

Device and circuit trends in gigabit logic

A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.

An E-beam fabricated GaAs D-type flip-flop IC

An E-Beam Fabricated GaAs D-Type Flip-Flop IC

A new monolithically integrated GaAs decision circuit has been fabricated in order to satisfy speed requirements of a 840 Mbit/s coaxial cable PCM transmission system. The circuit is of SSI complexity (about 60 integrated components) and utilizes normally-on type MESFETs with 0.75-mu n gate length, exhibiting a cutoff-frequency f/sub T/ = 20 GHz. The main features of the circuit performance are: high clock frequency capability (up to 3 GHz), 100-ps rise- and fall-times, high dynamic sensitivity (65 mV peak-to-peak over a 1 GHz bandwidth), and moderate power consumption (350 mW typically). The described IC is able to drive low impedance transmission lines (output signal 600 mV/50 omega) and can be used for multilevel signal regeneration in the 1-2 Gbit/s range.

G. Nuzillat

Papers

An E-beam fabricated GaAs D-type flip-flop IC

An E-Beam Fabricated GaAs D-Type Flip-Flop IC

A Monolithic GaAs Decision Circuit for Gbit/s PCM Transmission Systems