Open Access
An E-beam fabricated GaAs D-type flip-flop IC
M. Gloanec,G. Nuzillat,C. Arnodo,M. Peltier +3 more
- Vol. 80, pp 472-478
TLDR
In this article, a first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was developed, leading to logic gates with propagation delays in the range 130-170 ps.Abstract:
A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.read more
Citations
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Journal ArticleDOI
GaAs MESFET ICs for gigabit logic applications
G. Nuzillat,E.H. Perea,G. Bert,F. Damay-Kavala,M. Gloanec,M. Peltier,Tung Pham Ngu,C. Arnodo +7 more
TL;DR: The present status of speed-power performances, packing densities, and integration levels is presented on the basis of some MSI and LSI MESFET IC realizations made possible by the principal GaAs logic approaches to date.
Journal ArticleDOI
Low pinch-off voltage f.e.t. logic (l.p.f.l.): I.s.i. oriented logic approach using quasinormally off GaAs m.e.s.f.e.t.s.
TL;DR: A new l.p.f.e.s.i.t.l. logic approach, leading to highly versatile logic gates capable of combining high speed and low power consumption and requiring a standard fabrication process, is introduced and structures of complex logic gates realisable with this approach are described.
Proceedings ArticleDOI
Microwave Integrated Circuits on GaAs
TL;DR: A review of the present status of MMICs is given with special reference to the specific advantages and problems of monolithic microwave circuits as opposed to hybrid circuits in this article, where some applications are also discussed together with perspectives of future progress in the field.
Proceedings ArticleDOI
GaAS Digital ICs for High-Speed Signal Processing
TL;DR: This paper reviews the basic concepts of digital signal processing, the principal functions needed by special-purpose hardware implementation, and the main features and present status of high-speed digital GaAs ICs technology with some illustrations of potential applications in future radar and telecommunication systems.
Journal ArticleDOI
Electron-beam fabricated high-speed digital GaAs integrated circuits
TL;DR: In this article, the fabrication and performance of high-speed GaAs logic circuits incorporating submicrometer gate length FET's fabricated by electron-beam lithography is discussed.
References
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High-speed integrated logic with GaAs MESFET's
R.L. Van Tuyl,C. Liechti +1 more
TL;DR: In this article, the feasibility of using GaAs metal-semiconductor field effect transistors (GaAs MESFETs) in fast switching and high-speed digital integrated circuit applications is demonstrated.
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Journal ArticleDOI
Planar GaAs IC technology: Applications for digital LSI
R.C. Eden,B.M. Welch,R. Zucca +2 more
TL;DR: Schottky diode-FET logic (SDFL) as mentioned in this paper utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements.
Journal ArticleDOI
Femtojoule high speed planar GaAs E-JFET logic
Abstract: An integrated inverter stage operating in the gigabit range at a static power dissipation of 100 µW was built for future use in LSI logic circuits. Planar gallium arsenide technology was employed using selective ion-implanted enhancement mode junction field-effect transistors (E-JFET) having 3-µm gate lengths. A nine-stage ring oscillator served as a test vehicle to assess the speed-power product for digital applications. A theoretical analysis shows the transistor operates during the switching transient in the saturation regime, notwithstanding steady-state operation in the linear regime. When the transistor is switched off, the transient response is governed by the load resistance and the input capacitance of the subsequent stage. Means of reducing the switching time by increasing the supply voltage, nonlinear load devices, an output buffer stage, and reduction of gate length and width are described. Directly coupled E-JFET logic does not require level shifting, and, therefore, offers advantages over depletion-mode gallium arsenide MESFET logic by reducing the number of circuit elements per gate. Projected gallium arsenide E-JFET LSI logic circuits will surpass silicon-based bipolar logic with respect to both speed and power, and n-channel silicon MOS logic with respect to speed.