Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dual-metal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate- and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of fT and fMAX values, whereas the channel-engineered device exhibits a reduction of fT by 2.7% with nearly equal fMAX.

Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs

Effect of gate engineering in double-gate MOSFETs for analog/RF applications

An analytical model for tunnel barrier modulation in triple metal double gate tunnel FET is presented for the first time in this paper. Three different metals over the channel region assist to form a barrier in the channel which restricts the reverse tunneling of the carrier, i.e., tunneling from drain to source. The choice of three metals with different work functions helps to increase the ON-current and also to form a barrier in the channel, which reduces the OFF-current. The surface potential and the electric field are analytically modeled by solving 2-D Poisson’s equation and Kane’s model is used to calculate the tunneling current. The analytical results are verified with SILVACO ATLAS simulated results.

An Analytical Model for Tunnel Barrier Modulation in Triple Metal Double Gate TFET

A 2-D analytical model for the surface potential and threshold voltage of graded-channel dual-material double-gate (GCDMDG) MOSFETs obtained by intermixing the concepts of graded doping in channel and dual material in gate engineering has been proposed. The parabolic approximation method has been explored for determining the potential distribution function of the device by solving Poisson’s equation with suitable boundary conditions. The threshold voltage roll-off, drain-induced barrier lowering and lateral electric field have also been examined. The effects of different device parameters on device performance have been evaluated to check its figure-of-merit over the graded-channel double-gate (GCDG) and dual-material double-gate (DMDG) structures. For validation of the proposed model, the results have been compared with the numerical simulation data obtained by ATLAS™, a 2-D device simulator from SILVACO.

2-D Analytical Modeling of Threshold Voltage for Graded-Channel Dual-Material Double-Gate MOSFETs

In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, Dual Material Double Gate (DMDG) SOI MOSFET, exhibits significantly reduced short channel effects when compared with the DG SOI MOSFET. Short channel effects in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage and drain induced barrier lowering. A model for the drain current, transconductance, drain conductance and voltage gain is also discussed. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation

https://web.iitd.ac.in/~mamidala/HTMLobj-168/MEJ_sept04.pdf

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect-transistor (MOSFET) in which the front gate consists of two materials with different work functions.

https://web.iitd.ac.in/~mamidala/HTMLobj-347/JJAP_09_05.pdf

Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential

https://web.iitd.ac.in/~mamidala/HTMLobj-184/MEE04.pdf

Evidence for suppressed short-channel effects in deep submicron dual-material gate (DMG) partially depleted SOI MOSFETs - A two-dimensional analytical approach

G. Venkateshwar Reddy

Papers

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential

Evidence for suppressed short-channel effects in deep submicron dual-material gate (DMG) partially depleted SOI MOSFETs - A two-dimensional analytical approach