An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Introduction to flash memory

This paper reviews the basic physical mechanisms of the interactions of ionizing radiation with MOS oxides, including charge generation, transport, trapping and detrapping, and interface trap formation. Device and circuit effects are also discussed briefly.

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Total ionizing dose effects in MOS oxides and devices

Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs.

Radiation Effects in MOS Oxides

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by ionizing radiation exposure have diminished by aggressive semiconductor scaling, the question remains whether there may be unknown, potentially worse threats lurking in the deep submicron regime. This manuscript provides a basic overview of some of the materials, devices, and designs that are being explored or, in some cases, used today. An overview of radiation threats and how radiation effects can be characterized is also presented. Last, the paper provides a detailed discussion of what we know now about how modern devices and materials respond to radiation and how we may assess, through the use of advanced analysis and modeling techniques, the relative hardness of future technologies

Total-Ionizing-Dose Effects in Modern CMOS Technologies

Low-field leakage current has been measured in thin oxides after exposure to ionising radiation. This Radiation Induced Leakage Current (RILC) can be described as an inelastic tunnelling process mediated by neutral traps in the oxide, with an energy loss of about 1 eV. The neutral trap distribution is influenced by the oxide field applied during irradiation, thus indicating that the precursors of the neutral defects are charged, likely to be defects associated with trapped holes. The maximum leakage current is found under zero-field condition during irradiation, and it rapidly decreases as the field is enhanced, due to a displacement of the defect distribution across the oxide towards the cathodic interface. The RILC kinetics are linear with the cumulative dose, in contrast with the power law found on electrically stressed devices.

Radiation induced leakage current and stress induced leakage current in ultra-thin gate oxides

MOS capacitors with a 4.4 nm thick gate oxide have been exposed to /spl gamma/ radiation from a Co/sup 60/ source. As a result, we have measured a stable leakage current at fields lower than those required for Fowler-Nordheim tunneling. This Radiation Induced Leakage Current (RILC) is similar to the usual Stress Induced Leakage Currents (SILC) observed after electrical stresses of MOS devices. We have verified that these two currents share the same dependence on the oxide field, and the RILC contribution can be normalized to an equivalent injected charge for Constant Current Stresses. We have also considered the dependence of the RILC from the cumulative radiation dose, and from the applied bias during irradiation, suggesting a correlation between RILC and the distribution of trapped holes and neutral levels in the oxide layer.

Ionizing radiation induced leakage current on ultra-thin gate oxides

A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC

The excess leakage current across ultra-thin dielectrics has been studied for different ionizing radiation sources. Namely, X-rays, 8 MeV electrons, and three ion beams with different LETs values have been used on large area MOS capacitors with 4-nm thick oxides. Small oxide fields were applied during irradiation, reaching 3 MV/cm at most. For ionizing radiation with relatively low LET (<10 MeV cm/sup 2//mg), only Radiation Induced Leakage Current (RILC) was observed, due to the formation of neutral defects mediating electron tunneling via a single oxide trap. For high LET values, instead, the gate leakage current could be described by an empirical relation proper of Soft Breakdown (SB) phenomena detected after electrical stress. Moreover, the typical random telegraph signal noise feature of this Radiation induced Soft Breakdown (RSB) currents was observed during and after irradiation. RSB can be attributed to conduction through a multi-defect path across the oxide, produced by the residual damage of dense ion tracks. The oxide field applied during irradiation enhances the RSB intensity, but RSB can be achieved even for irradiation at zero field, being LET the main factor leading to RSB activation. The dose dependence of both RILC and QB have been investigated, showing a quasi linear kinetics with the cumulative dose. We have also studied the effect of modifying the angle of incidence of the ion beam on the intensity of the gate leakage current.

Low field leakage current and soft breakdown in ultra-thin gate oxides after heavy ions, electrons or X-ray irradiation

An analytical model of Radiation Induced Leakage Current (RILC) has been developed for ultra-thin gate oxides submitted to high dose ionizing radiation. The model is based on the solution of the Schrodinger equation for a simplified oxide band structure, where RILC occurs through electron trap-assisted tunneling. The values of the model parameters have been calibrated by comparing the transmission probabilities obtained in this model with those obtained through the WKB method in the actual oxide band structure. No free fitting parameter has been introduced, and all physical constant values have been selected within the values found in literature. Different trap distributions have been considered as candidates, but the comparison between simulated and experimental curves have indicated that a double gaussian distribution in space and in energy grants the best fit of the experimental results for different ionizing particles, oxide fields during irradiation, radiation doses, and oxide thickness. Excellent matching has been found for both positive and negative RILC by using a single trap distribution. The trap density linearly increases with the radiation dose and decreases with the oxide field during irradiation. The trap distribution is spatially symmetrical in the oxide, centered in the middle of the oxide thickness, and is not modified as the cumulative dose increases.

Gabriella Ghidini

Papers

Radiation induced leakage current and stress induced leakage current in ultra-thin gate oxides

Ionizing radiation induced leakage current on ultra-thin gate oxides

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC

Low field leakage current and soft breakdown in ultra-thin gate oxides after heavy ions, electrons or X-ray irradiation

A model of radiation induced leakage current (RILC) in ultra-thin gate oxides