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Gerard Ghibaudo

Researcher at University of Grenoble

Publications -  1063
Citations -  18362

Gerard Ghibaudo is an academic researcher from University of Grenoble. The author has contributed to research in topics: MOSFET & Threshold voltage. The author has an hindex of 53, co-authored 1036 publications receiving 16706 citations. Previous affiliations of Gerard Ghibaudo include University of Savoy & Micro and Nanotechnology Innovation Centre.

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Journal ArticleDOI

New method for the extraction of MOSFET parameters

TL;DR: In this article, a new method for the extraction of the MOSFET parameters is presented, which relies on combining drain current and transconductance transfer characteristics, enabling reliable values of the threshold voltage V/sub t/, the low field mobility mu /sub 0/ and the mobility attenuation coefficient theta to be obtained.
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Improved Analysis of Low Frequency Noise in Field‐Effect MOS Transistors

TL;DR: In this article, an improved analysis of low frequency trapping noise in a MOS device is proposed, taking into account the supplementary fluctuations of the mobility induced by those of the interface charge, which enables an adequate description of the gate voltage dependence of the input equivalent gate voltage noise to be obtained in various actual situations.
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Review on high-k dielectrics reliability issues

TL;DR: In this article, the authors review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results, showing that the reliability of Hf-based materials is influenced both by the interfacial layer as well as the high k layer.
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Electrical noise and RTS fluctuations in advanced CMOS devices

TL;DR: An overview of recent issues concerning the low frequency (LF) noise in modern CMOS devices is given and the approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental results obtained on advanced CMOS generations.
Proceedings ArticleDOI

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

TL;DR: In this article, the Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter) is extended to an independent double gate memory architecture, called φ-Flash.