The OpenCL standard offers a common API for program execution on systems composed of different types of computational devices such as multicore CPUs, GPUs, or other accelerators.

/pdf/opencl-a-parallel-programming-standard-for-heterogeneous-508iki5i96.pdf

OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems

Big data

We propose a new set of OS abstractions to support GPUs and other accelerator devices as first class computing resources. These new abstractions, collectively called the PTask API, support a dataflow programming model. Because a PTask graph consists of OS-managed objects, the kernel has sufficient visibility and control to provide system-wide guarantees like fairness and performance isolation, and can streamline data movement in ways that are impossible under current GPU programming models. Our experience developing the PTask API, along with a gestural interface on Windows 7 and a FUSE-based encrypted file system on Linux show that the PTask API can provide important system-wide guarantees where there were previously none, and can enable significant performance improvements, for example gaining a 5× improvement in maximum throughput for the gestural interface.

/pdf/ptask-operating-system-abstractions-to-manage-gpus-as-3nimx5ultu.pdf

PTask: operating system abstractions to manage GPUs as compute devices

Printed circuit board

Thermal management and temperature uniformity enhancement of electronic devices by micro heat sinks: A review

A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side

Semiconductor chip with reinforcing through-silicon-vias

This continuing exploration of GPU technology examines ATI Stream technology and its use in scientific and engineering applications.

Scientific and Engineering Computing Using ATI Stream Technology

2.5D packages have been widely used in electronics industry for high performance and product miniaturization. As Through-Silicon-Via (TSV) fabrication methods and multi-level assembly technologies get mature, 2.5D packaging becomes reliable and affordable. In this work, board-level life prediction was performed for a 2.5D Field-Programmable Gate Array (FPGA) assembly in both accelerated thermal cycling and power cycling. Finite element models were built and validated by warpage measurement. Solder fatigue life in power cycling was investigated by computational fluid dynamics (CFD) simulation and finite element analysis. Improved life prediction for power cycling was achieved by mapping temperature results from CFD model to finite element model. Parametric studies regarding geometry and material factors were performed including PCB, substrate, thermal interface material (TIM) and lid adhesive, to give design suggestions to improve board-level thermal reliability. Maximum junction temperature of a 2.5D FPGA package is dependent on application scenarios and working environment. It is found that the designed maximum junction temperature and applied heatsink clamping force have considerable influences on board-level reliability.

Comprehensive Study on 2.5D Package Design for Board-Level Reliability in Thermal Cycling and Power Cycling

A semiconductor device includes first and second stacked semiconductor dies on a substrate. A lid having a plurality of fins extending downwardly into the cavity is mounted on the substrate to encapsulate the semiconductor dies. At least some of the fins are longer than other ones of said fins. The lid is attached to the substrate, with the longer fins extending downwardly above a region of the substrate not occupied by the first die. The shorter fins extend downwardly above a region of said first die not covered by said second die. A thermal interface material fills the remainder of the cavity and is in thermal communication with both dies, the substrate and the fins. The lid may be molded from metal. The lid may be bonded to the topmost die, using a thermal bonding material that may be liquid metal, or the like.

Multi-die semiconductor package with heat spreader

Advanced packaging for high end field programmable gate array (FPGA) applications, such as data center and emulation, has recently focused on silicon interposers to enable higher transistor counts and increasing bandwidth, leading to increased power and larger packages, up to 55 mm x 55 mm. The increasing complexity, larger package size, and smaller pitches which enable these advancements pose mechanical challenges such as warpage and reliability. To accommodate the increased power, a stiffener ring may replace the lid. High bandwidth memory (HBM) offers significant performance gain in the form of a vertical stack of memory chips. However, the use of a stiffener ring and incorporation of HBM exacerbate the warpage and reliability challenges, especially as package sizes continue to increase. This work studies the design constraints upon these large packages and to find that reliable packages may be achieved. This work starts by introducing the current options for advanced packaging of an FPGA. The 2.5D silicon interposer structure was selected and the current structure for an FPGA was designed, fabricated, and tested. Warpage was measured with DIC, -40 to 125 °C thermal cycling reliability tests were conducted through 1200 cycles, and high temperature storage tests at 150 °C were conducted for 2000 hours. Through these reliability experiments, the primary mechanical challenges associated with the design space were identified to be thermal cycling and warpage. Finite element models were built and validated using warpage data. Design parameters including ring material, ring size, and substrate CTE were analyzed for their effect on warpage and reliability. Then, a second design was created by optimizing tradeoffs to meet the warpage requirement and improve reliability as much as possible. The second design passed all warpage and reliability requirements.

Gamal Refai-Ahmed

Papers

Semiconductor chip with reinforcing through-silicon-vias

Scientific and Engineering Computing Using ATI Stream Technology

Comprehensive Study on 2.5D Package Design for Board-Level Reliability in Thermal Cycling and Power Cycling

Multi-die semiconductor package with heat spreader

Warpage and Reliability Challenges for Stacked Silicon Interconnect Technology in Large Packages