The organization of behavior: A neuropsychological theory

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory

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Art of electronics

In the last few years, the deep learning (DL) computing paradigm has been deemed the Gold Standard in the machine learning (ML) community. Moreover, it has gradually become the most widely used computational approach in the field of ML, thus achieving outstanding results on several complex cognitive tasks, matching or even beating those provided by human performance. One of the benefits of DL is the ability to learn massive amounts of data. The DL field has grown fast in the last few years and it has been extensively used to successfully address a wide range of traditional applications. More importantly, DL has outperformed well-known ML techniques in many domains, e.g., cybersecurity, natural language processing, bioinformatics, robotics and control, and medical information processing, among many others. Despite it has been contributed several works reviewing the State-of-the-Art on DL, all of them only tackled one aspect of the DL, which leads to an overall lack of knowledge about it. Therefore, in this contribution, we propose using a more holistic approach in order to provide a more suitable starting point from which to develop a full understanding of DL. Specifically, this review attempts to provide a more comprehensive survey of the most important aspects of DL and including those enhancements recently added to the field. In particular, this paper outlines the importance of DL, presents the types of DL techniques and networks. It then presents convolutional neural networks (CNNs) which the most utilized DL network type and describes the development of CNNs architectures together with their main features, e.g., starting with the AlexNet network and closing with the High-Resolution network (HR.Net). Finally, we further present the challenges and suggested solutions to help researchers understand the existing research gaps. It is followed by a list of the major DL applications. Computational tools including FPGA, GPU, and CPU are summarized along with a description of their influence on DL. The paper ends with the evolution matrix, benchmark datasets, and summary and conclusion.

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Review of deep learning: concepts, CNN architectures, challenges, applications, future directions

In recent years the concept of chaos-based computing has emerged as a way to harness the rich state space of chaotic systems for robust computation. Potential advantages of such chaotic computational elements include improved security in the form of logic obfuscation and power analysis mitigation. For example, the chaotic nature of computation leads to a chaotic power profile that is difficult to use for side-channel attacks. In this paper, we explore the construction of chaotic logic gates based on Chua's circuit. We propose a two-dimensional chaotic logic gate that utilizes the two state variables of Chua's circuit to implement all possible two-input logic functions. Further, the likelihood of any logic function is shown to approach 1/16 as the evolution time of the gate is increased. Equally likely functions are beneficial from a security perspective in that the power profile and potentially the logic itself can be obfuscated from potential attackers. It is difficult to determine the effective logic function without knowledge of past states.

A two-dimensional chaotic logic gate for improved computer security

The authors report on the realisation of an encryption process in real-time analogue circuitry using on-the-shelf components and minimal processing power. Self-synchronisation of two similar systems through a single shared state is a unique property of the chaotic Lorenz attractor system. In this process, the single parameters of the system are modulated to mask a message before transmitting securely through a single-shared state. However, these techniques are vulnerable to the return map attack. They show that time-scaling can further obfuscate the modulation process and improve return map attack immunity and demonstrate a fabricated printed circuit board implementation of the system.

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Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry

In neuromorphic computing, memristors (or "memory resistors'') have been primarily studied as key elements in artificial synapse implementations, where the memristor provides a variable weight with intrinsic long-term memory capabilities, based on its modifiable resistive-switching characteristics. Here, we demonstrate an efficient methodology for simulating resistive-switching of HfO2 memristors within Synopsys TCAD Sentaurus -- a well established, versatile framework for electronic device simulation, visualization and modeling. Kinetic Monte Carlo is used to model the temporal dynamics of filament formation and rupture wherein additional band-to-trap electronic transitions are included to account for polaronic effects due to strong electron-lattice coupling in HfO2. The conductive filament is modeled as oxygen vacancies which behave as electron traps as opposed to ionized donors, consistent with recent experimental data showing p-type conductivity in HfOx films having high oxygen vacancy concentrations and ab-inito calculations showing the increased thermodynamic stability of neutral and charged oxygen vacancies under conditions of electron injection. Pulsed IV characteristics are obtained by inputting the dynamic state of the system -- which consists of oxygen ions, unoccupied oxygen vacancies, and occupied oxygen vacancies at various positions -- into Synopsis TCAD Sentaurus for quasi-static simulations. This allows direct visualization of filament electrostatics as well as the implementation of a nonlocal, trap-assisted-tunneling model to estimate current-voltage characteristics during switching. The model utilizes effective masses and work functions of the top and bottom electrodes as additional parameters influencing filament dynamics. Together, this approach can be used to provide valuable device- and circuit-level insight, such as forming voltage, resistance levels and success rates of programming operations, as we demonstrate.

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TCAD Modeling of Resistive-Switching of HfO2 Memristors: Efficient Device-Circuit Co-Design for Neuromorphic Systems

In this paper, we implemented a lightweight reconfigurable pseudo-random number generator (PRNG). The map generates discrete-time chaotic signals. The chaotic oscillator requires two map circuits to generate chaotic signals. The design is reconfigurable because two map circuits have two bifurcation parameters which can be leveraged to generate multiple random sequences. The design of the PRNG utilizes two chaotic oscillators, analog mux, 10 bit ADC, 2 bit shift register and an XOR gate. The circuit has been implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The estimated power consumption of the circuit is 2.12 mW and the area overhead is 0.132 mm2. The throughput of the proposed PRNG is 100 MS/s. The proposed PRNG can be used for security applications in IoT devices which requires circuits with less area and power overhead. The PRNG design passes all the tests in NIST SP 800-22 test suite.

Design of a Lightweight Reconfigurable PRNG Using Three Transistor Chaotic Map

In this paper we present a memristive neuromorphic system for higher power and area efficiency. The system is based on a mixed signal approach considering the digital nature of the peripheral and control logics and the integration being analog. So, the system is connected digitally outside but the core is purely analog. This mixed signal approach provides the advantage of implementing neural networks with spiking events in a synchronous way. Moreover, the use of nano-sclae memristive device saves the area and power of the system and some considerations about the the device have also been proposed in the paper to make the system more energy efficient.

https://par.nsf.gov/servlets/purl/10073171

Garrett S. Rose

Papers

A two-dimensional chaotic logic gate for improved computer security

Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry

TCAD Modeling of Resistive-Switching of HfO2 Memristors: Efficient Device-Circuit Co-Design for Neuromorphic Systems

Design of a Lightweight Reconfigurable PRNG Using Three Transistor Chaotic Map

A mixed-signal approach to memristive neuromorphic system design