The organization of behavior: A neuropsychological theory

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory

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Art of electronics

In the last few years, the deep learning (DL) computing paradigm has been deemed the Gold Standard in the machine learning (ML) community. Moreover, it has gradually become the most widely used computational approach in the field of ML, thus achieving outstanding results on several complex cognitive tasks, matching or even beating those provided by human performance. One of the benefits of DL is the ability to learn massive amounts of data. The DL field has grown fast in the last few years and it has been extensively used to successfully address a wide range of traditional applications. More importantly, DL has outperformed well-known ML techniques in many domains, e.g., cybersecurity, natural language processing, bioinformatics, robotics and control, and medical information processing, among many others. Despite it has been contributed several works reviewing the State-of-the-Art on DL, all of them only tackled one aspect of the DL, which leads to an overall lack of knowledge about it. Therefore, in this contribution, we propose using a more holistic approach in order to provide a more suitable starting point from which to develop a full understanding of DL. Specifically, this review attempts to provide a more comprehensive survey of the most important aspects of DL and including those enhancements recently added to the field. In particular, this paper outlines the importance of DL, presents the types of DL techniques and networks. It then presents convolutional neural networks (CNNs) which the most utilized DL network type and describes the development of CNNs architectures together with their main features, e.g., starting with the AlexNet network and closing with the High-Resolution network (HR.Net). Finally, we further present the challenges and suggested solutions to help researchers understand the existing research gaps. It is followed by a list of the major DL applications. Computational tools including FPGA, GPU, and CPU are summarized along with a description of their influence on DL. The paper ends with the evolution matrix, benchmark datasets, and summary and conclusion.

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Review of deep learning: concepts, CNN architectures, challenges, applications, future directions

The focus of the field of molecular electronics in recent years has been mostly limited to the development of molecular electronic test devices and the characterization of electron transport through organic molecules. However, in order for molecular electronic technology to be realized, it is probable that these devices will have to first be integrated with traditional CMOS components and circuits. For this reason, we present the design of a molecular device/CMOS hybrid circuit that exemplifies how the two technologies can be integrated as well as how the CMOS circuitry can be used for the on-chip characterization of the molecular electronic devices. This work includes: the fabrication and characterization of a silicon-based CMOS-compatible molecular electronic device, the design of a hybrid circuit that can be used for on-chip characterization of the molecular devices, and simulations based upon the actual experimental device results that verify the effectiveness of the circuit. The components in this preliminary work have been limited to simple example devices and circuits to serve as a proof of concept, but the basic framework can be expanded in the future to include much more complex behaviors and systems.

On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results

We present a technique to improve the distinguishability of the stored memory states in a memristive (resistive) random-access memory (ReRAM) cell, utilizing controlled phase transitions in an augmented threshold switch (TS). Oxide memristors exhibit significant device-to-device and cycle-to-cycle variations between the low and high resistive states. This leads to degraded distinguishability during the read operation and makes it challenging to design sense amplifiers. To circumvent this major issue, here we propose to augment volatile threshold switches with the ReRAM cell and trigger selective phase transitions to enhance the overall cell resistance ratio. We first analyze the biasing constraints to successfully implement our technique in a memristive memory cell. We keep the TS in the metallic state during write operations. Whereas for read operations, we ensure that the TS remains in the insulating (metallic) state when the memristor in the ReRAM is in high (low) resistance state. With proper co-design, our technique can improve the read current ratio and sense margin of conventional ReRAM cells by up to $\sim 10\mathbf{X}$ and $\sim 5\mathbf{X}$ (respectively), with iso-cell area. Our approach has negligible impact on the write performance, contingent upon the appropriate choice of TS and memristor pair.

Threshold Switch Assisted Memristive Memory with Enhanced Read Distinguishability

A MOS-JFET macromodel of silicon-on-insulator (SOI) four-gate transistor (G4FET) is presented in this paper to facilitate innovative circuit design with this novel multi-gate transistor. Designing interesting and innovative circuits with any new device requires a SPICE model that will work sufficiently well throughout the desired operating regions. A macromodel approach is adopted in this work which can provide a reasonably fast and accurate circuit simulation. Since G4FET combines the functionality of MOSFET and JFET devcies and robust, fast and reliable models of both MOSFET and JFET are already available, a macromodel combining these existing models is desirable from the perspective of a circuit designer. The model captures the essential interaction between multiple gates and accounts for both the volume and the surface conduction. In order to justify the feasibility of the macromodel, it is used to simulate two analog multiplier circuits which have been previously demonstrated experimentally and the simulation results match quite well with experimental findings.

A MOS-JFET Macromodel of SOI Four-Gate Transistors (G 4 FET) to Aid Innovative Circuit Design

—In this paper, we introduce RISP , a reduced instruction spiking processor. While most spiking neuroprocessors are based on the brain, or notions from the brain, we present the case for a spiking processor that simpliﬁes rather than complicates. As such, it features discrete integration cycles, conﬁgurable leak, and little else. We present the computing model of RISP and highlight the beneﬁts of its simplicity. We demonstrate how it aids in developing hand built neural networks for simple computational tasks, detail how it may be employed to simplify neural networks built with more complicated machine learning techniques, and demonstrate how it performs similarly to other spiking neurprocessors.

The Case for RISP: A Reduced Instruction Spiking Processor

Neuromorphic computing systems are alternatives to conventional microprocessors, often built from unconventional hardware. Designing and evaluating these systems requires multiple levels of simulation, from the device level to the circuit level to the system level. In this paper, we describe the system level simulator of a neuromorphic computing system based on memristors. We compare it to a circuit level simulator of the same system, both verifying its accuracy and demonstrating its performance improvement. We argue that system level simulation is an essential part of the design process of neuromorphic systems.

Garrett S. Rose

Papers

On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results

Threshold Switch Assisted Memristive Memory with Enhanced Read Distinguishability

A MOS-JFET Macromodel of SOI Four-Gate Transistors (G 4 FET) to Aid Innovative Circuit Design

The Case for RISP: A Reduced Instruction Spiking Processor

High-Level Simulation for Spiking Neuromorphic Computing Systems