A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

System and method for making a LDMOS device with electrostatic discharge protection

This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.

A Review on the ESD Robustness of Drain-Extended MOS Devices

While silicon controlled rectifiers (SCRs) are highly robust electrostatic discharge (ESD) protection devices, they typically are not suited for high-voltage ESD protection due to their inherently low holding voltage and thus vulnerability to latch-up threat. In this letter, a new high holding voltage dual-direction SCR (NHHVDDSCR) with a small area and optimized topology is developed in a 0.18- $\mu \text{m}$ CMOS technology. The results of the NHHVDDSCR and other SCR devices measured from the transmission line pulsing are compared and discussed. It is shown that the NHHVDDSCR can possess a relatively high and adjustable holding voltage, as well as an acceptable failure current for robust ESD protection of high voltage applications.

A New High Holding Voltage Dual-Direction SCR With Optimized Segmented Topology

Conductivity Modulation in Semiconductor Structures Under Breakdown and Injection.- Standard and ESD Devices in Integrated Process Technologies.- ESD Clamps.- ESD Network Design Principles.- ESD Design for Signal Path Analog.- Power Management Circuits' ESD Protection.- System-Level and Discrete Components ESD.

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ESD Design for Analog Circuits

Latchup immunity is a challenging issue for the design of power supply clamps used in high-voltage electrostatic discharge (ESD) protection applications. While silicon-controlled rectifiers (SCRs) are highly robust ESD devices, they are traditionally not suited for high-voltage ESD due to their inherent low holding voltage and, thus, vulnerability to latchup. In this letter, a novel SCR stacking structure with an extremely high holding voltage, very small snapback, and acceptable failure current has been developed. The new and existing high holding voltage ESD devices are also compared to demonstrate the advancement of this work.

Silicon-Controlled Rectifier Stacking Structure for High-Voltage ESD Protection Applications

To avoid latch-up failure in high voltage integrated circuits, a source-side engineering technique for on-chip ESD protection nLDMOS is proposed in this work. Experimental results have been verified in a 0.5-µm 16-V bipolar CMOS DMOS technology. Measurement results from transmission-line-pulsing system show that the proposed source-side engineering method can effectively increase the holding voltage of the nLDMOS from 10.5V to 16.2V. Transient-induced latch-up tests show that the proposed source-side engineering technique significantly improves the latch-up immunity of nLDMOS in on-chip ESD protection circuit.

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Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mum 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.

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Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.

Devices without current crowding effect at the finger's ends

An ESD protection device. The ESD protection device is incorporated with a gap structure in a laterally diffused metal oxide semiconductor (LDMOS) field effect transistor, isolating a doped region and a field oxide region. When a parasitical semiconductor controlled rectifier (SCR) of LDMOS is turned off, ESD current is discharged distributively through several discharge paths, avoiding ESD current focus in a signal narrow discharge path and the danger therefrom.

LDMOS transistor with improved ESD protection

With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-µm 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.

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Geeng-Lih Lin

Papers

Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

Devices without current crowding effect at the finger's ends

LDMOS transistor with improved ESD protection

Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection