A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Flash EEprom system

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Highly compact EPROM and flash EEPROM devices

In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a non-volatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.

Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Flash EEPROM System with Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks

A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an “original” location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a “moved” location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the “original” physical block address and the “moved” physical block address and for providing information regarding “moved” sectors within the block being accessed.

Moving sectors within a block of information in a flash memory mass storage architecture

A memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory (30). The assignment of the replacement locations in the alternate memory is made on a selective basis taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code which is used in connection with the memory system. A relatively small writable index, which is addressed by a subset of the main memory address signals, provides a partial address and control fields to the alternate memory in accordance with control data transferred from the host system. Control data is developed by the host system each time it is powered on and is based on identifying each defective location in main memory through a diagnostic routine and analyzing the defect distribution in a way to provide control signals which minimize the number of replacements that are assigned and maximize the number of data words that can be transferred from the memory system to the host system before an uncorrectable error is encountered by the ECC system.

Memory system with selective assignment of spare locations

A fault alignment exclusion method and apparatus is disclosed which operates to prevent the alignment of two or more defective bit storage locations at an address in a memory array. The disclosed memory comprises a plurality (n×m) of separate memory chips arranged in a matrix of n rows and m columns. Each of the chips contains a large plurality (64K) of individually addressable bit locations. A plurality of data words, each containing m (72) bit positions are transferred from the memory array to a n (16) word m (72) bit position buffer during a memory read operation. Steering logic responsive to control signals is disposed between the memory and the buffer which permits the n chips in each column of the array to be effectively rearranged selectively within the respective columns so that the relationship of any given chip to a position of the 16 storage positions in a corresponding buffer column may be selectively changed by the control signals applied to the steering logic. The control signals are developed based on defect data stored in an error map such that each memory address contains no more than one defective location.

Multi-bit error scattering arrangement to provide fault tolerant semiconductor static memories

The makeup of memory words is controlled by a memory address permutator that permits up to 2 n ! input bit combinations. The particular combinations used in any decoder is dependent on the particular application. The new permutator also permits scattering of certain faults throughout the usable memory address space while simultaneously accumulating other faults in deallocated sections of the memory.

Fault alignment control system and circuits

Circuit for eliminating the effect of contact bounce

A fault alignment exclusion method and apparatus is disclosed which operates to prevent the alignment of two or more defective bit storage locations at an address in a memory array. The disclosed memory comprises a plurality (n x m) of separate memory chips (71) arranged in a matrix of n rows and m columns. Each of the chips contains a large plurality (64K) of individually addressable bit locations. A plurality of data words, each containing m (72) bit positions are transferred from the memory array to a n' (16) word m (72) bit position buffer during a memory read operation. Steering logic (35) responsive to control signals (R5-R8) is disposed between the memory and the buffer which permits the n (32) chips in each column of the array to be effectively rearranged selectively within the respective columns so that the relationship of any given chip to a position of the 16 storage positions in a corresponding buffer column (20) may be selectively changed by the control signals applied to the steering logic. The control signals are developed based on defect data stored in an error map such that each memory address contains no more than one defective location. An additional control signal (R2) may be used to control an address permutation logic (40) for helping to achieve the same purpose.

George Leroy Bond

Papers

Memory system with selective assignment of spare locations

Multi-bit error scattering arrangement to provide fault tolerant semiconductor static memories

Fault alignment control system and circuits

Circuit for eliminating the effect of contact bounce

Multi-bit error scattering arrangement to provide fault tolerant semiconductor memory