Patent
Memory system with selective assignment of spare locations
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TLDR
In this article, a memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory, taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code used in connection with the memory system.Abstract:
A memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory (30). The assignment of the replacement locations in the alternate memory is made on a selective basis taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code which is used in connection with the memory system. A relatively small writable index, which is addressed by a subset of the main memory address signals, provides a partial address and control fields to the alternate memory in accordance with control data transferred from the host system. Control data is developed by the host system each time it is powered on and is based on identifying each defective location in main memory through a diagnostic routine and analyzing the defect distribution in a way to provide control signals which minimize the number of replacements that are assigned and maximize the number of data words that can be transferred from the memory system to the host system before an uncorrectable error is encountered by the ECC system.read more
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References
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Patent
Defect-tolerant digital memory system
TL;DR: In this paper, a defect-tolerant memory system has been proposed for determining when memory operations are addressed to locations that are defective, and for directing these operations to spare memory locations in a main memory.
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Method for providing a substitute memory in a data processing system
TL;DR: In this paper, a method for substituting one memory module for another, faulty, memory module comprises designating and marking a memory module as the substitute module, which, upon detection of a fault in the other memory module, is inhibited from responding to its own address when called, and responds to the address of the faulty module whenever the latter is called.
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Memory sparing arrangement
TL;DR: In this article, a digital data processing arrangement for providing automatic substitution of a spare memory module for a malfunctioning portion of the system memory is disclosed, which takes place in a manner transparent to the software programs being run in the processing system.
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Error logging in semiconductor storage units
TL;DR: In this article, a maintenance procedure comprising a method of and an apparatus for storing information identifying the location of one or more defective bits, i.e., a defective memory element, a defective storage device or a failure, in a single-errorcorrecting semiconductor main storage unit (MSU) comprised of a plurality of large scale integrated bit planes.
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Apparatus for accessing an information storage device having defective memory cells
TL;DR: An information storage device comprising an information storage unit consisting of a plurality of memory blocks each consisting of memory cells, and means for storing therein the address information uniquely corresponding to said memory blocks including some inoperative memory blocks is defined in this paper.