A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of $19.8\cdot 10^{-3}\ \text{mm}^{2}$ and is powered from 0.7 V with a standby current consumption of around 36 $\mu\text{A}$ . DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.

0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier

This paper presents a CMOS operational transconductance amplifier (OTA), suitable for sub-1-V supply applications, whose (input) common-mode voltage can be set to ( $V_{\mathrm {\mathbf {DD}}}+V_{\mathrm {\mathbf {SS}}})$ /2 thanks to two combined techniques applied to the differential pair, namely, threshold voltage lowering and elimination of the tail current generator. Both techniques are implemented through a single common-mode feedback loop, which embeds the shared bulk terminal of the pair. In contrast to other low-voltage approaches employing bulk driving, the proposed OTA is driven from the gate terminals and exploits only MOS transistors in strong inversion. Therefore, effective values of dc gain, gain bandwidth, and noise are found, suitable for high-accuracy switched-capacitor applications. Using a standard 0.35- $\mu \text{m}$ technology with nominal MOS transistors threshold around 0.7 V, a 0.9-V OTA with 0.45-V analog ground was designed and successfully tested. The measured gain and unity gain frequency were 65 dB and 1 MHz with phase margin of 60° for a capacitive load of 10 pF.

0.9-V Class-AB Miller OTA in 0.35- $\mu \text{m}$ CMOS With Threshold-Lowered Non-Tailed Differential Pair

This brief presents a low-power, area-efficient three-stage CMOS operational transconductance amplifier (OTA) suitable for very large capacitive loads, ${C} _{L}$  A single Miller capacitor and an inverting current buffer embedded in the input stage are exploited to implement the frequency compensation network An additional feed-forward path and a slew rate enhancer are also utilized to improve the large-signal transient response Detailed small-signal analysis reveals that the proposed OTA does not exhibit an upper limit of drivable ${C} _{L}$  The OTA is fabricated in a standard 035- ${\mu }\text{m}$ technology and occupies 00027 mm2 of die area Under 14-V supply and 636- ${\mu }\text{A}$ quiescent current consumption, it provides a dc gain greater than 110 dB and is stable for any ${C} _{L}$ larger than 5 nF Comparison with the state of the art shows remarkable improvement of both small- and large-signal performance

High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of ${C}_{L}$

A class AB version of the conventional super source follower (SSF) is described. The circuit greatly increases slew rate (SR) and current efficiency, maintaining the low distortion and low output resistance of the SSF. Class AB operation is achieved without extra power dissipation or supply requirements, and without bandwidth or noise degradation. The circuit can advantageously replace the SSF in a wide variety of analog systems, opening a new research line in analog design. To illustrate the widespread application of this cell, a class AB differential unity-gain buffer, a class AB differential current mirror and two class AB differential transconductors are designed, fabricated in a 0.5µm CMOS technology and tested. Measurement results using a dual supply of ±1.65V show that the proposed class AB version of the SSF improves SR by a factor 21.5 and increases bandwidth by 10%, keeping noise level, input range, power consumption, and supply requirements unaltered. The fabricated class AB current mirror features a THD at 100 kHz of − 62dB for signal currents 20 times larger than the bias current. The fabricated transconductors feature an IM3 at 1 MHz of − 56.6dB for output currents more than 13 times larger than the bias currents. Copyright © 2011 John Wiley & Sons, Ltd.

Power-efficient analog design based on the class AB super source follower

SUMMARY

A second-generation current conveyor with digitally programmable current gains is presented. A current division network with zero standby power consumption is utilized in two different ways to provide both gain and attenuation of the second-generation current conveyor's current transfer characteristics. The proposed topology overcomes several drawbacks of the previous solutions through affording a more power and area efficient solution while exhibiting relatively wider tuning range and bandwidth. A variable-gain amplifier and a two-integrator-loop filter biquad providing low-pass and band-pass responses are given as application examples. A modified two-integrator-loop topology is developed to offer independent control of the pole frequency and quality factor without disturbing the passband gain. Simulation results obtained from a standard 0.18 µm complementary metal–oxide semiconductor process are given. Copyright © 2011 John Wiley & Sons, Ltd.

A complementary metal–oxide semiconductor digitally programmable current conveyor

A compensation technique for low-power three-stage operational transconductance amplifiers is presented in this paper. The compensation network is made up of passive components and entails only one Miller capacitor. Design equations describing the amplifier behavior for different capacitive load conditions are reported along with three design examples for different capacitive loads, namely, 1 nF, 100 and 10 pF. The amplifier exhibits a gain-bandwidth product equal to 2.48, 6.74 and 7.66 MHz in the three cases while dissipating only 150, 150 and 57.5 μW from 2.5 V, respectively. Simulation results are found in good agreement with theoretical analysis and show an improvement in both small-signal and large-signal amplifier performance over many previously reported solutions.

Improved single-miller passive compensation network for three-stage CMOS OTAs

High-speed CMOS unity-gain current amplifier

A power-efficient frequency compensation technique for four-stage transconductance amplifiers is proposed. Stability analysis and design equations are carried out based on the small-signal model. To verify the effectiveness of the compensation scheme, a four-stage amplifier is designed in a standard CMOS 65-nm technology. The compensation exploits passive components only and is implemented without entailing extra transistors, thus saving circuit complexity and power consumption. The amplifier achieves a 19-MHz gain-bandwidth product when driving a 1-nF capacitance by consuming only 80 μW from a 1-V supply. Simulation results show a significant improvement in both small-signal and large-signal amplifier performance with respect to prior art.

High-performance frequency compensation topology for four-stage OTAs

This article presents useful guidelines for designing CMOS class-AB output stages. Three Quality Factors, which allow analysis and comparison of different output stages, are used to design two CMOS class-AB stages. We show that using the proposed Quality Factors and the related strategy leads to an efficient design in terms trade-off among area, current consumption, bandwidth and distortion. Indeed, for one of the two stages adopted as example, the design through the Quality Factors results in superior distortion performance with respect to the design suggested in the original article. Design examples and simulations are provided to validate the design strategy.

Design guidelines of CMOS class-AB output stages: a tutorial

Summary

A continuous-time complementary metal–oxide–semiconductor differential pair that does not require the traditional tail current source as a way to control the direct current and common-mode current is presented. Compared with a p-channel long-tailed pair, the proposed non-tailed solution operates under a higher maximum input common-mode voltage that includes (VDD + VSS)/2 even under low supply voltages. Experimental measurements on a prototype fabricated in a 0.35-µm technology (with metal–oxide–semiconductor thresholds greater than 0.6 V) confirm this behavior for supply voltages as low as 1.2 V, whereas the long-tailed pair with the same technology offers the same capability only for supplies higher than 1.6 V. Copyright © 2015 John Wiley & Sons, Ltd.

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Giuseppe Di Cataldo

Papers

Improved single-miller passive compensation network for three-stage CMOS OTAs

High-speed CMOS unity-gain current amplifier

High-performance frequency compensation topology for four-stage OTAs

Design guidelines of CMOS class-AB output stages: a tutorial

CMOS Non-tailed differential pair