Showing papers in "Analog Integrated Circuits and Signal Processing in 2016"
TL;DR: In this paper, a memristor emulator circuit with off-the-shelf electronic devices is presented, consisting of three operational transconductance amplifiers (OTA) and four second generation current conveyors (CCII).
Abstract: In this paper, memristor emulator circuit which is built with off the shelf electronic devices is presented. It consists of three operational transconductance amplifiers (OTA) and four second generation current conveyors (CCII). Using OTA offers an extra control parameter, operational transconductance parameter (gm), in addition to frequency (f) and amplitude value of voltage across emulator (vm). Since gm is proportional to current flowing through the bias terminal of OTA, it is possible to change the memristance variation via a simple change of amplitude value. Since gm parameter is adjustable via an external dc voltage/current source, the memristance of presented emulator circuit is electronically tuneable. Mathematical model is derived to characterize the behaviour of the emulator circuit. Frequency analysis is performed to determine how to maintain the pinched hysteresis loop at high frequencies. The presented emulator circuit is simulated with SPICE simulation program. The breadboard experiment of emulator circuit is built using CA3080 and AD844 ICs for OTA and CCII devices respectively. Frequency dependent pinched hysteresis loop in the current versus voltage plane holds up to 10 kHz. Mathematical model and theoretical analyses show a good agreement with SPICE simulation and experimental test results.
93 citations
TL;DR: In this article, a new circuit for practical emulation of a floating memristor is presented, which is simple, flexible and built around the current-feedback operational-amplifier.
Abstract: In this paper a new circuit for practical emulation of a floating memristor is presented. The circuit is simple, flexible and built around the current-feedback operational-amplifier and avoids the use of analog-to-digital and digital-to-analog converters and the analog multiplier. The circuit is simpler than the very few available similar circuits. The application of the proposed floating memristor emulator in designing an FM-to-AM converter confirms the functionality of the proposed circuit. Experimental results are included.
53 citations
TL;DR: In this article, the authors presented novel energy-efficient switching schemes for a successive approximation register analog-to-digital converter, where the average switching energy is reduced by 99.21 and 99.37 % for the signal-independent and signal-dependent common mode voltage at the comparator, respectively.
Abstract: This letter presents novel energy-efficient switching schemes for a successive approximation register analog-to-digital converter. The new switch method consumes no switching energy in the first three comparison cycles. The average switching energy is reduced by 99.21 and 99.37 % for the signal-independent and signal-dependent common mode voltage at the comparator, respectively. A 75 % reduction in the total capacitance over the conventional scheme is also achieved. The variation of the common mode voltage at the comparator input in the proposed architecture is 50 % less than in other low power switching schemes.
44 citations
TL;DR: In this paper, a new technique to design and analyze a multi-phase oscillator is proposed based on the fractional-order elements or constant phase elements in order to generate equal or different phase shifts.
Abstract: Recently, multi-phase oscillator design witnesses a lot of progress in communication especially phase shift keying based systems. Yet, there is a lack in design multi-phase oscillator with different fractional phase shifts. Thus, in this paper, a new technique to design and analyze a multi-phase oscillator is proposed. The proposed procedure is built based on the fractional-order elements or constant phase elements in order to generate equal or different phase shifts. The general characteristics equation for any oscillator is studied to derive expressions for the oscillation conditions and oscillation frequency. Also, stability analysis is introduced to guarantee the oscillation. Then, different examples of oscillators for equal and different phase shifts are introduced with their simulations.
35 citations
TL;DR: Wang et al. as discussed by the authors proposed to use the statistical property features of transformed signals by the fractional Fourier transform in the optimal fractional order domain as fault features, such as range, mean, standard deviation, skewness, kurtosis, entropy, median, third central moment, and centroid.
Abstract: Feature extraction plays an important role in the field of fault diagnosis of analog circuits. How to effectively extract fault features is crucial to diagnostic accuracy. The components tolerance and circuit nonlinearities of analog circuits can cause some part overlapping of primal signal among different component faults in time domain and frequency domain. Currently, the existing method aims at wavelet features, statistical property features, conventional frequency features and conventional time-domain features. There is no decoupling ability for the feature extraction methods mentioned above. To solve the problem, a new fault features extraction method is proposed. The diagnostic results are compared with those from other methods. Firstly, it is proposed to use the statistical property features of transformed signals by the fractional Fourier transform in the optimal fractional order domain as fault features, such as range, mean, standard deviation, skewness, kurtosis, entropy, median, the third central moment, and centroid. And then, KPCA is used to reduce the dimensionality of candidate features so as to obtain the optimal features. Next, normalization is applied to rescale input features. Finally, extracted features are trained by SVM to diagnose faulty components in analog circuits. The simulation results show that compared with traditional methods, the proposed method is quite efficient to improve diagnostic accuracy.
35 citations
TL;DR: In this paper, a novel design of basic ternary logic gates using memristor is introduced, which is a set of AND, OR, inverters, NOR, and NAND gates.
Abstract: This paper introduces a novel design of basic ternary logic gates using memristor, which is a set of AND, OR, inverters, NOR, and NAND gates. The ternary logic is a promising alternative to the conventional binary logic design technique. The resistive-load MOSFET-based ternary logic gates have already been proposed. The proposed memristor-based circuit replaces the large resistors by employing active load memristor in the ternary logic gates. The proposed ternary logic circuits are shown to have great significant advantages relative to other known binary circuits and ternary circuits like low power dissipation, chip area, component count, dense fabrication and cost. The paper concludes with an implementation of the ternary logic gates using SPICE simulations.
35 citations
TL;DR: In this article, an ultra-low-power two-stage operational transconductance amplifier (OTA) with full rail-to-rail input/output swing is presented, which consists of composite transistors, improved bulk-driven folded cascode (FC) structure, feed-forward compensation path and high speed current mirrors.
Abstract: In this paper by using Gm-C compensation technique, an ultra-low-power two-stage operational transconductance amplifier (OTA) with full rail-to-rail input/output swing is presented. The proposed configuration consists of composite transistors, improved bulk-driven folded cascode (FC) structure, feed-forward compensation path and high-speed current mirrors. In comparison with the typical FC, the proposed input stage structure has the benefit of transconductance enhancement with the same power consumption without adversely affecting the noise and offset performance. The presented OTA is simulated in 0.18 μm CMOS technology and the simulation results confirm the theoretical analyses. The proposed amplifier exhibits a DC gain enhancement of 9.5 dB as well as 100 % improvement in gain-bandwidth compared to the conventional FC input stage structure. Finally, the amplifier consumes 400 nW @ 0.6 V supply voltage which makes it suitable for ultra-low-power applications.
32 citations
TL;DR: In this article, the authors present a 0.25 µm BiCMOS Technology bandpass filter implementation based on a single transistor Active Inductor (AI) with a compensation network that allows to control both the inductance and its series resistance value.
Abstract: In this paper we present a 0.25 µm BiCMOS Technology bandpass filter implementation based on a single transistor Active Inductor (AI). The high-Q AI integrated circuit is designed by the use of a single transistor with a compensation network that allows to control both the inductance and its series resistance value. The AI-based high frequency bandpass filter has a center frequency of 2000 MHz (useful for radio and radar applications) and a 3 dB bandwidth of about 6 MHz with a quality factor of about 330. Moreover, a discrete prototype of the same AI has been also designed and measured. Measurements results on the discrete board have shown a 3 dB bandwidth of about 10 MHz, a noise figure of 6 dB, a ?10 dBm P1 dB compression point with 80 dB dynamic range. The power supply is 1.2 V with a power consumption of 800 µW showing low-voltage low-power operation capability together with good general performances.
31 citations
TL;DR: In this article, the authors describe a new current mode implementation of Chua's circuit using differential voltage current conveyor transconductance amplifier (DVCCTA) and standard passive components like resistor, capacitor and active inductor.
Abstract: This research paper describes a new current mode implementation of Chua's circuit using differential voltage current conveyor transconductance amplifier (DVCCTA) and standard passive components like resistor, capacitor and active inductor. The Chua's circuit brings a verity of complex dynamical nature with Chaos that provides a wide range of bifurcation phenomena and attractors. The circuit 4schematic is simple but the nature of its outcome is vigorous and attractive. The existence of hidden chaotic nature is illustrated with the use of negative nonlinear resistor. Nonlinear negative resistor as well as active inductor used in the circuit is proposed using DVCCTA block. Simulations are performed by using PSPICE based ORCAD 16.6 circuit simulator to visualize various responses of the Chua's circuit. The DVCCTA building block is implemented using 0.25 μm TSMC CMOS technology. The simulated results agree well with the theoretical predictions. To validate the workability, the proposed circuit is also experimentally verified using commercially available IC AD844.
31 citations
TL;DR: In this article, the authors proposed a high speed CMOS hybrid comparator with reduced delay time and improved energy efficiency, which includes two stages with three stacked transistors, which are suitable for low-voltage operation.
Abstract: This paper presents a high speed CMOS hybrid comparator with reduced delay time and improved energy efficiency. The proposed hybrid comparator includes two stages with three stacked transistors which are suitable for low-voltage operation. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, while enhancing the positive feedback to reduce the discharging time in a low-power manner. The second quasi-dynamic latching stage uses NMOS input to gain the transconductance, thus reducing the latching time with negligible static power, while needing no additional clock signal. Therefore, the delay time and energy per conversion are both significantly reduced in the proposed hybrid comparator. Measurement results in 40-nm CMOS process show that the proposed hybrid comparator operates up to 6 GHz with 61.08-ps delay time. The power consumption is 345.9 $$\upmu $$μW at 1.1-V supply, while the occupied die area is 64.5 $$\upmu $$μm$$^2$$2 (7.5 $$\upmu $$μm $$\times $$× 8.6 $$\upmu $$μm).
26 citations
TL;DR: A new decision tree approach for analog circuit fault diagnosis using binary support vector machines (BSVMs) that are trained by using different data sets that achieves better performance in terms of accuracy and efficiency than existing approaches.
Abstract: This paper proposes a new decision tree approach for analog circuit fault diagnosis using binary support vector machines (BSVMs) that are trained by using different data sets. To evaluate the performance of those different BSVMs, a new criterion is defined by considering the weighted number of fault-pairs that can be separated by one BSVM. Specifically, the weight of each fault-pair is inversely proportional to the number of BSVMs that can separate it. Simulation results by using two example circuits demonstrate that the proposed approach achieves better performance in terms of accuracy and efficiency than existing approaches.
TL;DR: In this paper, two topologies of voltage mode third order quadrature oscillator circuit using operational transresistance amplifier (OTRA) are presented, one based on low-pass filter and integrator combination, whereas the other one is high-pass filtering and differentiator combination.
Abstract: In this paper, the authors present two topologies of voltage mode third order quadrature oscillator circuit using operational transresistance amplifier (OTRA). The first circuit is based on low-pass filter and integrator combination, whereas the second one is high-pass filter and differentiator combination. Both the circuits utilize two OTRAs and three resistors and capacitors each. The frequency of oscillation and condition of oscillation can be adjusted independent of each other in both the circuits. The non-ideality analysis of the circuits are also included. The PSPICE simulation and experimental results verify the theoretical proposition.
TL;DR: The proposed architecture relaxes the design of the notch filter and the analog-to-digital converter (ADC) used in building the EEG detection system and has a total gain ranging from 61 to 84 dB, a total power dissipation of 32 µW and input referred noise spectral density of 4-µV.
Abstract: This paper proposes a configurable analog front-end (AFE) chain architecture used in the EEG detection system. The proposed chain consists of three stages: the first and the third stages are instrumentation amplifier and programmable gain amplifier, respectively, and the second stage is notch filter with low pass feature. The proposed architecture relaxes the design of the notch filter and the analog-to-digital converter (ADC) used in building the EEG detection system. A basic building block is the digitally programmable balanced output operational transconductance amplifier (DPOTA), which is proposed to realize the AFE blocks. A successive-approximation ADC (SA-ADC) architecture is mostly designed on digital circuits in order to lower the power dissipation. Based on this, PSpice post layout simulation results for the overall EEG detection system using 0.25-µm CMOS technology are also given. The overall configurable gain/filtering chain architecture has a total gain ranging from 61 to 84 dB, a total power dissipation of 32 µW and input referred noise spectral density of 4 µV/ $$\sqrt {\text{Hz}}$$Hz.
TL;DR: In this paper, two different voltage mode frequency agile filters employing voltage differencing trans-conductance amplifier (VDTA) are designed for encrypted communications and implemented by CMOS technology to benefit from easy and cheaper manufacturing of CMOS circuits.
Abstract: In this study, two different voltage mode frequency agile filters employing voltage differencing trans-conductance amplifier (VDTA) are designed for encrypted communications. The agility of the designed frequency agile filters are supported by only switching transistors instead of feedback systems in the conventional designs. The proposed frequency agile filters are implemented by CMOS technology to benefit from easy and cheaper manufacturing of CMOS circuits. One of the designed frequency agile filter is realized by changing gm (trans-conductance) and the other is realized by varying capacitance. The MOS capacitor technique is used instead of conventional capacitors in the second frequency agile filter structure. The CMOS performance of designed frequency agile filter realized with VDTA is compared with the recently recommended frequency agile filter structure realized with Bi-CMOS technology. The performance parameters of the VDTA and agile filter structures are summarized and the suitability of the filters for different applications are given. The designed filter can be easily operated up to 1 GHz. In this study, HAVEQUICK operating UHF band between 225 and 400 MHz is selected as the essential application of the designed filters. Moreover, proposed structures are laid-out. To prove the performance of the designed frequency agile filters, post-layout simulations with Monte Carlo and corner analyses are performed as well. AMS 0.18 µm parameters are used for the CMOS realization of the designed frequency agile filter.
TL;DR: In this paper, a wideband linearized common-gate low-noise amplifier (LNA) is proposed, where the linearity is improved by active cross-coupled feedback technique.
Abstract: A wideband linearized common-gate low-noise amplifier (LNA) is proposed. The linearity is improved by active cross-coupled feedback technique. The active cross-coupled feedback circuit, consisting of a complementary source follower and a feedback capacitor, is employed to enhance loop gain, and acquire linearity improvement. A passive cross-coupled feedback removes the second-order harmonic feedback effect to the input-referred third-order intercept point (IIP3). An enhanced LC-match input network and forward isolation of the active cross-coupled feedback enable the proposed LNA with wideband input matching and flat gain performance, respectively. Fabricated in a 0.13 μm RF CMOS process, the LNA achieves a flat voltage gain of 14.5 dB, an NF of 2.5---3.4 dB, and an IIP3 of 3.1---4.3 dBm over a 3 dB bandwidth of 0.1---1.2 GHz. It consumes only 3.5 mA from a 1.2 V supply and occupies an area of 0.2 mm2.
TL;DR: In this paper, a new topology and design methodology for ultra-low noise and high-gain transimpedance amplifiers is proposed for TIA circuits. But, the authors do not consider the effect of DC dark current of the input photodiodes.
Abstract: This paper reports on a new topology and design methodology for ultra-low noise and high-gain transimpedance amplifiers. This paper also reports on measurement results of two implemented ICs based on the proposed topology and fabricated in 130 nm IBM and 180 nm TSMC technologies. A capacitive feedback topology is implemented as a noise-efficient feedback network, analytical noise calculations in this family of TIA circuits are presented, and optimum noise criterion is derived. The saturation and instability problem of TIA circuits resulted from DC dark current of the input photodiodes is also addressed and a simple yet efficient feedback solution is proposed. The measurement results of 130 nm chip show average input referred noise of 2.67 pA/?Hz with bandwidth of 81 kHz to 1.76 GHz and transimpedance gain of 76 dB? while dissipating 13.7 mW from a 1.5 V power supply, including the output buffer. The measurement results of 180 nm chip show average input referred noise of 3.18 pA/?Hz with bandwidth of 72 kHz to 1.62 GHz and transimpedance gain of 75 dB? while dissipating 26.3 mW from a 2.2 V power supply, including the output buffer.
TL;DR: In this paper, a new tunable floating active inductor based on a modified tunable grounded active inductors is proposed, where the multi-regulated cascade stage is used in the proposed active structure to decrease the parasitic series resistance of active inducter, thus the Q factor enhancement is obtained.
Abstract: In this paper, a new tunable floating active inductor based on a modified tunable grounded active inductor is proposed. The multi regulated cascade stage is used in the proposed active structure to decrease the parasitic series resistance of active inductor, thus the Q factor enhancement is obtained. Furthermore, the arrangement of this stage leads to the smaller input transistor which determines active inductor's self-resonance frequency and to be free of body effect which is crucial in sub-micron technology. Symmetrical design strategy has enabled both ports of the proposed floating active inductor to demonstrate the same properties. The Q factor and active inductor value are tuned with bias current and flexible capacitance (varactor), respectively. The self-resonance frequency of floating active inductor (~6.2 GHz) is almost the same as grounded prototype. In addition, the proposed active inductor also shows higher quality factor and inductance value compared to the conventional floating active inductor circuits. To show the performance of suggested circuit, simulations are done by using a 0.18 µm CMOS process, which demonstrates an adjustable quality factor of 10---567 with an inductance value range of 6---284 nH. Total DC power consumption and occupied area are 2 mW and 934.4 µm2, respectively.
TL;DR: In this article, a systematic design approach based on noise optimization with power consumption minimization for operational transconductance amplifiers (OTAs) is presented, where HSPICE and ACO algorithm are used as simulation tool and optimization method, respectively.
Abstract: In this paper, a systematic design approach based on noise optimization with power consumption minimization for operational transconductance amplifiers (OTAs) is presented. In this methodology, HSPICE and ant colony optimization (ACO) algorithm are used as simulation tool and optimization method, respectively. By re-writing the thermal noise, flicker noise, corner frequency and other specifications of the OTA based on the Gm/Id characteristic in all regions of transistor operation, noise optimization beside the power minimization is achieved in a reasonable simulation time. In this approach, ACO is applied in order to optimize the design variables, aim at minimizing the input referred noise and power consumption. The design methodology is successfully used for systematic design and optimization of a CMOS Miller folded cascade amplifier using 0.18 µm CMOS technology in the three regions of amplifier operation. Simulation results confirm the accuracy of the theoretical analysis in the presented design methodology.
TL;DR: In this paper, the authors presented a behavioral model for amorphous indium-gallium-zinc oxide thin-film transistor using artificial neural network (ANN) based equivalent circuit (EC) approach to predict static and dynamic behavior of the device.
Abstract: This paper presents a behavioral model for amorphous indium---gallium---zinc oxide thin-film transistor using artificial neural network (ANN) based equivalent circuit (EC) approach to predict static and dynamic behavior of the device. In addition, TFT parasitic capacitances (CGS and CGD) characterization through measurements is also reported. In the proposed model, an EC is derived from the device structure, in terms of electrical lumped elements. Each electrical element in the EC is modeled with an ANN. Then these ANNs are connected together as per the EC and implemented in Verilog-A. The proposed model performance is validated by comparing the circuit simulation results with the measured response of a simple common-source amplifier, which has shown 12.2 dB gain, 50 μW power consumption and 85 kHz 3-dB frequency with a power supply of 6 V. The same circuit is tested as an inverter and its response is also presented up to 50 kHz, from both simulations and measurements. These results show that the model is capable of capturing both small and large signal behavior of the device to good accuracy, even including the harmonic distortion of the signal (that emphasizes the nonlinear behavior of the parasitic capacitance), making the model suitable for IC design.
TL;DR: In this article, a compact power amplifier matched by a proposed lowpass filter with nth harmonics suppression is presented, where the LPF is applied as an output transformer network, which transforms 50 Ω to the desired impedance to have maximum power.
Abstract: A compact power amplifier matched by a proposed lowpass filter (LPF) with nth harmonics suppression is presented in this paper. In the proposed PA, the LPF is applied as an output transformer network, which transforms 50 Ω to the desired impedance to have maximum power. In this method the conventional output matching network is eliminated, which results in the 26 % size reduction of the proposed PA as compared with the conventional one. Moreover, using the LPF at the output impressively suppresses the harmonics (2nd---5th) with high levels of attenuation. The proposed PA is designed at the 2.6 GHz, which is suitable for LTE applications. The simulated and measured results are in the good agreement, which confirm the validity of the proposed design.
TL;DR: Values strongly suggest that interictal phase EEG of an epileptic patient is less complex and more predictable compared to normal EEG, and support vector machine (SVM) classifier was implemented based on both sub-band energies and chaotic features extracted from EEG.
Abstract: In this study, we have reinvestigated the chaotic features and sub-band energies of EEG and its ability for aiding neurologists in detecting epileptic seizures. The study was done on the EEG of ictal and interictal phases of epileptic patients and of normal subjects. The EEG was decomposed using discrete wavelet transform to obtain various sub-bands and the chaotic features like correlation dimension and largest Lyapunov exponent were extracted. The analysis results clearly show that the correlation dimension and largest Lyapunov exponent have their lowest value during seizure activity, higher for interictal and even higher values for normal EEG. These values strongly suggest that interictal phase EEG of an epileptic patient is less complex and more predictable compared to normal EEG. Chaotic features extracted are potential parameters for automated diagnosis of epilepsy. Support vector machine (SVM) classifier was implemented based on both sub-band energies and chaotic features extracted from EEG. Classification performance parameters of SVM classifier based on sub-band decomposed energies and chaotic features were calculated.
TL;DR: A high linearity energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) and improves the linearity of SAR ADC.
Abstract: A high linearity energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Monotonic switching scheme and split-capacitor technique are combined. This scheme has no reset energy consumption, and achieves purely 98.05 % less switching energy and 75 % reduction of the total capacitance over the conventional architecture. Moreover, the proposed scheme also improves the linearity of SAR ADC. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.116LSB and 0.083LSB, respectively. The proposed scheme achieves a well trade-off between energy and linearity.
TL;DR: In this paper, a double-tail latched comparator with a self-neutralization technique has been proposed for biomedical applications with a power-delay product of 0.0172 fJ at 100 kHz clock frequency.
Abstract: This paper presents a new ultra-low power double-tail latched comparator suited for biomedical applications. The proposed comparator benefits from a positive feedback to achieve high resolution with low kickback noise. It is shown by time analysis and simulation that the delay time is significantly reduced compared to a conventional double-tail latched comparator. The presented circuit is designed and simulated in 0.18-μm CMOS technology. The post-layout simulation results show that the designed comparator consumes only 1.56 nW power, at 600 mV supply voltage and 100 kHz clock frequency. This amount is 54.35 % of power consumption of a conventional double-tail latched comparator with the same input referred offset of 7.5 mV. Furthermore, the proposed circuit provides a self-neutralization technique which results 8.8 % reduction of kick-back noise in comparison to the conventional latched comparator. The maximum clock frequency of this circuit is 200 MHz at 1 V supply voltage. The proposed circuit has a power-delay product of 0.0172 fJ at 100 kHz clock frequency. The proposed comparator is well designed to operate with supply voltages between 400 mV and 1 V.
TL;DR: In this article, a wearable wrist sensor based on the neural network technique was used to estimate acoustic parameters 51 and S2 of the heart sounds using a wrist sensor, which can be analyzed and monitored in real time and potentially in a long term with a wrist device.
Abstract: The paper presents a new method to estimate acoustic parameters 51 and S2 of the heart sounds using a wearable wrist sensor based on the neural network technique. Using the new method, the heart conditions can be analyzed and monitored in real time and potentially in a long term with a wrist device. The velocities and time delays of the cardiac pulse waves in blood vessels were experimentally acquired and calculated at different artery locations on the human body. Signal attenuation of the pulses from the heart to the wrist artery was analyzed and a pulse-waveform transfer model in artery was proposed. A neural network with two layers and 500 tansig neurons was employed to emulate the inverse acoustic transfer function from the wrist to heart. Comparisons between the parameters of the original heart sounds and estimated cardiac sounds were made to verify the accuracy of the neural network. It is encouraging to find that the acoustic properties of the original and estimated heart sounds have an accuracy up to 100% and the heart rates have an accuracy up to 99%. Using the trained neural network, heart sounds were estimated from the wrist artery by connecting the wrist sensor to a Bluetooth audio module to implement a wearable heart sound estimator. Performance of the new estimation method was verified. The proposed wrist sensor aims as a wireless wearable monitor on wrists for continuous and long-term medical diagnosis and athlete performance monitoring.
TL;DR: The simulation results show that the design of adjustable memristor memristance/memductance provides tunable filter parameters and without any significant distortion with appropriate parameter set even at ultra-low power levels and at very-low frequencies.
Abstract: Memristor has been claimed as the passive fourth fundamental circuit element in 1971. About four decades later, a physical realization which presents memristor behavior has resulted in significant interest on memristor and it is continuing to increase at a growing rate. Memristor can provide new possibilities in analog circuit design thanks to its properties which cannot be mimicked by older passive circuit elements. Since no practically available memristor exist on the market yet, obtaining of a practical implementation which behaves like a memristor is important from the point of view real-world circuit design. In this paper, an ultra low-voltage ultra low-power DTMOS-based memristor design is presented. Ultra low-voltage, ultra low-power operational amplifier and ultra low-voltage, ultra low-power multiplier are also designed to use in the implementation. Memristor design is composed of these two type active blocks using CMOS 0.18 µm process technology with symmetric ?0.25 V supply voltages. Our memristor is used in a second order Sallen---Key band-pass filter topology. Designed memristor-based Sallen---Key band-pass filter is then used for real electroencephalogram data processing. The simulation results show that the design of adjustable memristor memristance/memductance provides tunable filter parameters and without any significant distortion with appropriate parameter set even at ultra-low power levels and at very-low frequencies.
TL;DR: In this paper, the authors presented behavior level modeling to predict the frequency and displacement of electrostatic cantilever based microelectromechanical system sensor for mass detection using Linear Time Invariant (LTI) technique.
Abstract: In this work we present behavior level modeling to predict the frequency and displacement of electrostatic cantilever based microelectromechanical system sensor for mass detection. Linear time invariant (LTI) technique is used to study the linear and nonlinear behavior of the device. The shift in resonance frequency in damped and undamped medium is formulated by using the conception of dynamic mass and law of identity. First a complete analytical model is developed by coupling electrostatic force with the bending moment of cantilever to produce vertical actuation at a resonance frequency. Then displacement of the cantilever is correlated with piezoresistive mechanism for mass sensing. We assumed mass of blood cells as the external load on cantilever tip which results in shift in resonance frequency. Simulink tool is used to develop the LTI model that is based on electromechanical coupling of linear and nonlinear equations. The same device is then designed using COMSOL tool and FEM analysis is performed. For validation, the analytical results are compared with the FEM simulations.
TL;DR: In this article, a low-voltage, MOSFET-only, third order low-pass filter is proposed using TSMC 0.18 µm technology parameters and dynamic threshold voltage MOS tuning technique has been developed for the filter circuit to suppress the non-idealities.
Abstract: A new low-voltage, MOSFET-only, third order low-pass filter is proposed. The circuit employs only MOSFETs operating in saturation region. The transconductance gains and the parasitic gate to source capacitances of the MOSFETs represent resistive and capacitive elements of the filter. Using TSMC 0.18 µm technology parameters the circuit is simulated, non-ideal effects have been investigated and dynamic threshold voltage MOS tuning technique has been developed for the filter circuit to suppress the non-idealities. In this tuning technique, bulk terminals of MOS transistors are used to adjust the biasing point of the circuit by changing the threshold voltages of the MOS transistors. This gives the designers more flexibility than conventional tuning methods and allows low voltage operation when several transistors are stacked over each other. The resulting circuit is capable of operation at high frequencies with low power consumption due to the usage of significantly less number of transistors than conventional active block-based filtering circuits.
TL;DR: This paper introduces an evolutionary criterion based on genetic algorithm for the efficient simplification of symbolic PSRR expressions and shows that the proposed evolutionary-based simplification technique outperforms the existing simplification criteria.
Abstract: Parasitic interactions through the power supply lines put major limitations on the performance of analog amplifiers, especially in the mixed analog---digital integrated circuits. In this paper, a general method is presented for the symbolic analysis of power-supply rejection ratio (PSRR) in CMOS analog operational amplifiers. Since the complexity of the symbolic expressions grows exponentially with the circuit size, it is necessary to utilize simplification techniques for the analysis of practical circuits. We introduce an evolutionary criterion based on genetic algorithm for the efficient simplification of symbolic PSRR expressions. In contrast to the classical simplification criteria which simplify the different polynomials separately, the main advantage of the proposed criterion is to consider the correlation between different polynomials and different symbolic terms. The proposed methodology guarantees the accuracy of the simplified PSRR expressions in contrast to the exact ones, with a predictable error rate. Comparison of the numerical results extracted from the simplified symbolic PSRR expressions with HSPICE over two analog amplifiers demonstrates the efficiency of the proposed methodology. Simulations also show that the proposed evolutionary-based simplification technique outperforms the existing simplification criteria.
TL;DR: In this paper, a compensation technique for low-power three-stage operational transconductance amplifiers is presented, where the compensation network is made up of passive components and entails only one Miller capacitor.
Abstract: A compensation technique for low-power three-stage operational transconductance amplifiers is presented in this paper. The compensation network is made up of passive components and entails only one Miller capacitor. Design equations describing the amplifier behavior for different capacitive load conditions are reported along with three design examples for different capacitive loads, namely, 1 nF, 100 and 10 pF. The amplifier exhibits a gain-bandwidth product equal to 2.48, 6.74 and 7.66 MHz in the three cases while dissipating only 150, 150 and 57.5 μW from 2.5 V, respectively. Simulation results are found in good agreement with theoretical analysis and show an improvement in both small-signal and large-signal amplifier performance over many previously reported solutions.
TL;DR: In this paper, a CMOS current differencing transconductance amplifier (CDTA) with high transconductances has been proposed, where a cross coupled PMOS active load has been used in place of conventional active load.
Abstract: A CMOS current differencing transconductance amplifier (CDTA) with high transconductance has been proposed. The transconductance (gm) of CDTA is generally increased either by increasing the biasing current IB or by increasing the size of transistors used in differential pair and current mirror structures. The first technique leads to higher power dissipation and limited range of transconductance while the second limits the input/output swing and bandwidth of CDTA due to higher parasitic capacitances. In the proposed design of CDTA, a cross coupled PMOS active load has been used in place of conventional PMOS active load. The cross coupled PMOS active load forms a positive feedback which results in higher transconductance, wider tuning range and less power consumption without any limitations on input/output swing and bandwidth of the CDTA. Mentor Graphics Eldo simulation tool has been used to verify the performance of proposed CDTA with TSMC 0.18 µm technology parameters. A voltage/current mode oscillator circuit of third order has been designed by proposed CDTA.