This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2 Gbps at 10 iterations. The operating frequency is 950 MHz after synthesis and the chip area is 2.9 mm2.

High-throughput layered decoder implementation for quasi-cyclic LDPC codes

Channel coding may be viewed as the best-informed and most potent component of cellular communication systems, which is used for correcting the transmission errors inflicted by noise, interference, and fading. The powerful turbo code was selected to provide channel coding for mobile broad band data in the 3G UMTS and 4G long term evolution cellular systems. However, the 3GPP standardization group has recently debated whether it should be replaced by low density parity check (LDPC) or polar codes in 5G new radio, ultimately reaching the decision to adopt the LDPC code family for enhanced mobile broad band (eMBB) data and polar codes for eMBB control. This paper summarizes the factors that influenced this debate, with a particular focus on the application specific integrated circuit (ASIC) implementation of the decoders of these three codes. We show that the overall implementation complexity of turbo, LDPC, and polar decoders depends on numerous other factors beyond their computational complexity. More specifically, we compare the throughput, error correction capability, flexibility, area efficiency, and energy efficiency of ASIC implementations drawn from 110 papers and use the results for characterizing the advantages and disadvantages of these three codes as well as for avoiding pitfalls and for providing design guidelines.

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

In this paper, we propose an efficient low-complexity switch network design for reconfigurable low-density parity-check (LDPC) decoders. The proposed architecture leads to significant reductions in hardware complexity. Since the structured quasi-cyclic (QC) LDPC codes for most modern wireless communication systems include multiple code rates, various block lengths, and different sizes of submatrices, a reconfigurable LDPC decoder is desirable and the barrel shifter needs to be programmable. The Benes network cannot be optimized as the barrel shifter for a reconfigurable LDPC decoder when the input size of barrel shifter is not a power of 2. Also, it is not trivial to generate all the control signals on-the-fly for numerous 2 × 2 switches in the switch network. In this paper, a novel low-complexity switch network design is proposed, which can be used efficiently when the input size of barrel shifters is not a power of 2. Furthermore, we propose a novel algorithm to generate all the control signals, which can be implemented with a small size of lookup table (LUT) or a simple combination logic on-the-fly, using the properties that both the full-size switch network can be broken into two half-size switch networks and the barrel shifters for the structured QC LDPC decoders require only cyclic shifts. Compared with conventional Benes networks using a dedicated LUT or a complicated signal generating algorithm, the proposed architectures achieve significant hardware reductions in implementing the barrel shifters for reconfigurable LDPC decoders. In synthesis result using the TSMC 0.18-?m standard cell CMOS technology, the proposed switch network for a reconfigurable LDPC decoder of IEEE 802.16e and IEEE 802.11n can be implemented with an area of 0.772 mm2, which leads to a significant area reduction.

Low-Complexity Switch Network for Reconfigurable LDPC Decoders

We describe a fully reconfigurable low-density parity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that fits into the allocated memories while achieving high decoding throughput. Our VLSI implementation has been optimized for the IEEE 802.11 n standard and achieves a throughput of 780 Mbit/s with a core area of 3.39 mm2 in 0.18 mum CMOS technology.

Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes

There is an increasing need for configurable quasi-cyclic low-density parity-check (QC-LDPC) decoders that can support a family of structurally compatible codes instead of a single code. The key component in a configurable QC-LDPC decoder is a programmable circular-shift network that supports cyclic shifts of any size up to a predefined maximum submatrix size. This paper presents a QC-LDPC shift network (QSN), which has two key advantages over state-of-the-art solutions in recent literature. First, the QSN reduces the number of stages in the critical path, which improves the clock frequency and makes it scalable, particularly in a field-programmable gate array (FPGA)-based implementation where an interconnect delay is dominant. Second, the QSN's control logic is simple to generate and occupies a significantly smaller area. The QSNs for a variety of codes suitable for emerging applications are implemented, targeting both a 180-nm Taiwan Semiconductor Manufacturing Company Ltd. complimentary metal-oxide-semiconductor library and a Xilinx Virtex 4 FPGA. The proposed implementation is shown to be 2.1 times faster than the best known implementation in literature and requires almost eight times less control area. Furthermore, this paper presents analytical models of the critical-path and datapath complexity for arbitrary-sized submatrices and proves that the QSN indeed generates all the output combinations required for implementing reconfigurable QC-LDPC decoders.

QSN—A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders

This paper describes a scalable IP of a decoder for LDPC codes compliant to IEEE 802.1 In and running the well- known layered decoding algorithm. The decoder architecture is arranged in clusters of serial processing units, which are configurable to process all the codes in the standard and, at the same time, to support multiple frame decoding. An optimization methodology of the iteration latency is also described, which relates to the order of the messages updated by the processors, as well as to the sequence of layers the decoder goes through. The logic synthesis on 65 nm CMOS technology with low- power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 180 to 410 Mbps, and the power consumption being below 235 mW.

A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes

The need for circularly shifting an array of data is a distinguishing feature of decoders for structured low-density parity-check (LDPC) code, as a result of an efficient trade-off between performance and parallelisation of the elaborations, or throughput. Since the decoder must typically cope with blocks of data with different size, described is an efficient architecture of a reconfigurable multi-size circular shifting network, used to circularly shift an array with arbitrary size.

Multi-size circular shifting networks for decoders of structured LDPC codes

This paper describes a scalable architecture of a decoder for IEEE 80211n low-density parity-check (LDPC) codes The decoder runs the layered decoding algorithm and its architecture is arranged in clusters of serial functional units, which are configured to process all codes in the standard The decoder works in pipeline, and a very effective technique to re- arrange the sequence of its elaborations is proposed in order to minimize the iteration latency; this relates to the order of the messages input and output by the processing units, as well as the sequence of layers followed for decoding Moreover, memory optimization techniques have been applied to get a very efficient partitioning, allowing the pipeline of the operations The synthesis on 65 nm CMOS technology with low-power standard- cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 136 to 355 Mbps, and the power consumption being below 185 mW

A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes

A configurable Turbo-LDPC decoder comprising:
 A set of P> 1 Soft-Input-Soft-Output decoding units (DP 0 -DP P-1 ; DP i ) for iteratively decoding both Turbo- and LDPC-encoded input data, each of said decoding units having first (I 1 i ) and second (I 2 i ) input ports and first (O 1 i ) and second (O 2 i ) output ports for intermediate data; First and second memories (M 1 , M 2 ) for storing said intermediate data, each of said first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of said decoding units to the output and input ports of said first memory, and the second input and output ports of said decoding units to the output and input ports of said second memory

Flexible Channel Decoder

Low-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. This paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. The decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with serial processing units working in pipeline to reduce the latency. Particularly, two different architectures are considered, and their RTL/memory complexity tradeoffs are analyzed. The resulting design yields a throughput ranging from 93 to 497 Mbps by means of 15 iterations at the clock frequency of 400 MHz. Synthesis on 65 nm CMOS technology, shows a chip area less than 0.59 mm2, despite the high flexibility, which compares favourably with similar implementations.

Giuseppe Gentile

Papers

A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes

Multi-size circular shifting networks for decoders of structured LDPC codes

A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes

Flexible Channel Decoder

Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes