Glenn A. Rinne

TL;DR: In this article, an integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads.

TL;DR: In this article, the authors describe a process in which solder bumps (310a in Fig 3B) on one or more substrates (100) are expanded by reflowing additional solder (300) into the plurality of solder bumps.

TL;DR: The relentless progress of semiconductor integration is reducing the area required for circuits, and the area available for power and ground bumps on wafer-level chip-scale packages also shrinks and the bump current density is now approaching levels where electromigration is a significant reliability concern.

TL;DR: In this article, the ground, power, and signal pads are coupled to the substrate through active semiconductor devices (e.g., FETs, BJTs, etc.).

TL;DR: In this paper, a controlled-shaped reservoir provides additional solder to a bump in the flow step for increasing the volume of solder forming the solder bump, thus, the height of the resulting solder bump can be predetermined.