Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.

Optimization of cell subtypes in a hierarchical design flow

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

System and method for product yield prediction

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

A layout parasitic extraction system is disclosed. The present invention is a connectivity-based approach for extracting layout parasitics. The present invention creates a connectivity-based database, where geometries of a layout are organized by net. The present invention allows net-by-net extraction of layout parasitics using a connectivity-based database. Furthermore, a user can select a net or nets for extraction. The present invention outputs a database containing nets and their extracted layout parasitics. The present invention can create a netlist format file from a database containing nets and their extracted parasitics to allow back annotation of layout parasitics into a circuit schematic or for use for other software (possibly from a third-party).

Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach

A system and method for selectively simulating logic circuit designs in which a data tables generator receives information from a schematic entry program or netlist entry file and produces data tables for use by a simulator. A designer provides inputs to the data tables generator from a schematic entry program or a netlist entry file. The data tables generator generates from the information received a table of used integrated circuits and a table of their connections. A simulator then receives the output from the data tables generator and produces a design simulation program table that executes integrated circuit model subroutine stored in an integrated circuit model reference library and netlist subroutines stored in a netlist connectivity table. The system may also be used for testing logic circuits on a printed circuit board by capturing signals from a potentially defective logic section of the printed circuit board and feeding them into test points of the integrated circuit simulated by the computer simulator.

Simulation of selected logic circuit designs

A mixed mode simulation method and apparatus are provided for highly accurately simulating the total characteristics of a digital analyzed circuit portion and an analog analyzed circuit portion, which are both subjected to mixed mode simulation, in consideration of the influence exerted on the analog analyzed circuit portion by a current consumed by the digital analyzed circuit portion. More particularly, a current value of an equivalent circuit for current calculation modeled for providing the analog analyzed circuit portion with a current generated due to an operating state of the digital analyzed circuit portion realized by logic simulation is determined in synchronism with the logic simulation, and the equivalent circuit for current calculation derived thereby is composed with the analog analyzed circuit portion, and this composite circuit is subjected to circuit simulation.

Mixed mode simulation method and simulator

A circuit simulation method and apparatus for simulating the operation of semiconductor devices, including field effect transistors (FETs), on the basis of the mask layout pattern of each semiconductor device. A circuit simulation method is performed by a computer which includes a first step of determining an equivalent circuit of the semiconductor device from the mask layout patterns, and a second step of producing a signal indicative of the operation of the equivalent circuit determined by the first step. The equivalent circuit is determined by extracting resistive area patterns of the FETs and calculating resistance values of FET signal paths to obtain FET equivalent resistances. The resistive area patterns are divided into a series of rectangles which are converted to equivalent resistive elements to then be arranged so that an equivalent resistive value can be calculated.

Circuit simulation method for semiconductor device including field effect transistors

We have developed a hi ghly parallel and accelerated circuit simulator which produces precise results for large scale simulation. We incorporated multithreading in both the model and matrix calculations to achieve not only a factor of 10 acceleration compared to the defacto standard circuit simulator used worldwide, but also equal or exceed the performance of timing-based event -driven simulators with the accuracy which matches that of SPICE-based circuit simulation. For example, a 89K element DRAM CAS circuit simulation can be performed in under 38 minutes with timing accuracy error as little as 7 ps.

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A Parallel and Accelerated Circuit Simulator with Precise Accuracy

In verifying an LSI layout pattern, the whole layout pattern is converted into circuit data and a subcircuit to be verified is picked up and subjected to simulation. After converting the layout pattern into the transistor level circuit data, the transistor level circuit data is transformed into a logic gate level circuit data while judging a clocked gate included in the subcircuit. After picking up a subcircuit in a predetermined manner, an approximate load is connected to the interface port of the picked-up subcircuit.

Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 h, making this method 5 times more efficient than conventional methods.

Goichi Yokomizo

Papers

Mixed mode simulation method and simulator

Circuit simulation method for semiconductor device including field effect transistors

A Parallel and Accelerated Circuit Simulator with Precise Accuracy

Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern

A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling