An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

A typical common source cascode low-noise amplifier (CS-LNA) can be treated as a CS-CG two stage amplifier. In the published literature, an inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. In this work, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential cascode CS-LNA. It uses a smaller noise reduction inductor compared with the conventional inductor based technique. It can reduce the noise, improve the linearity and also increase the voltage gain of the LNA. The proposed technique is theoretically formulated. Furthermore, as a proof of concept, a 2.2 GHz inductively degenerated CS-LNA was fabricated using TSMC 0.35 mum CMOS technology. The resulting LNA achieves 1.92 dB noise figure, 8.4 dB power gain, better than 13 dB S11, more than 30 dB isolation (S12), and -2.55 dBm IIP3, with the core fully differential LNA consuming 9 mA from a 1.8 V power supply.

A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA

In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-mum CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP3 of -8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 muW, respectively.

Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures

This paper presents a wideband common-gate (CG) LNA architecture that overcomes the fundamental tradeoff between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure (NF) over the previously reported feedback amplifiers in a CG configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. An amplifier prototype was realized in 0.18-μm CMOS, operates from 1.05 to 3.05 GHz, and dissipates 12.6 mW from 1.8-V supply while occupying a 0.073-mm2 active area. The LNA provides 16.9-dB maximum voltage gain, 2.57-dB minimum NF, better than - 10-dB input matching, and - 0.7-dBm minimum IIP3 across the entire bandwidth.

Wideband Common-Gate CMOS LNA Employing Dual Negative Feedback With Simultaneous Noise, Gain, and Bandwidth Optimization

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.

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CMOS low-noise amplifier design optimization techniques

This paper reviews and analyzes two reported image-rejection (IR) low-noise amplifier (LNA) design techniques based on CMOS technology, i.e., the second-order active notch filer and third-order passive notch filter. The analyses and discussions are based on the quality factor of filters and the ability of the frequency control. As the solution to deal with the suitable on-chip filter, this paper proposes a new notch-filter topology that can overcome the limitations of the two previous reported studies. In addition, the LNA design method satisfying the power-cons-trained simultaneous noise and input matching, as well as the linearity optimization conditions is introduced. By using the proposed notch filter and proposed design methodology, an IR LNA used in the superheterodyne architecture is implemented. The proposed IR LNA, designed based on 0.18-mum CMOS technology with total current dissipation of 4 mA under 3-V supply voltage, is optimized for a 5.25-GHz wireless local area network with IF frequency of 500-MHz applications. The measurement results show 20.5-dB power gain, lower than 1.5-dB noise figure, -5-dBm input-referred third-order intercept point and an IR of 26 dB

Image-rejection CMOS low-noise amplifier design optimization techniques

An area efficient and symmetric dual-layer spiral inductor structure is proposed and evaluated in comparison with the conventional single-layer spiral inductors. Measurements show that, for a given silicon area, the dual-layer inductor provides nearly 4 time the inductance of the single-layer inductor, while the quality factor is up to 2 times higher. For the same amount of inductance the dual-layer inductors show comparable to higher quality factor depends on frequency of operation. This paper demonstrates that, contrary to the common understanding the dual-layer can be more useful for the RF integrated circuits than the conventional single-layered spiral inductors from the aspects of area efficiency and quality factor The proposed dual-layer inductor can also be used as a high-frequency choke.

Design and analysis of symmetric dual-layer spiral inductors for RF integrated circuits

Up-conversion mixer and driver amplifier for 80211a wireless LAN application are designed and fabricated on 018 CMOS technology The proposed up-conversion mixer adopts source degeneration transconductance stage to control the conversion gain, and driver amplifier uses cascode topology to control the gain and linearity The fabricated up-mixer shows -6 /spl sim/ 10 dB of conversion gain and -185 dBm of OP/sub -1dB/ at 10 dB gain, and the driver amplifier shows -8 /spl sim/8 dB of power gain and 2 dBm of OP/sub -1dB/ at 6 dB gain The up-mixer and the driver amplifier consume 12mA and 9mA from 18 V supply, respectively

A transmitter front-end design for 5GHz WLAN applications

A completely symmetric dual-level spiral inductor structure is proposed. The symmetry, area efficiency, the size dependence of the coupling factor, and the quality factors of the dual-level inductors are evaluated and compared with that of the single-level. This work demonstrates that, with most RF applications, the dual-level inductors are the better choice than the single-level. key words: spiral inductors, symmetric, RF ICs, quality factor

Gook-Ju Ihm

Papers

CMOS low-noise amplifier design optimization techniques

Image-rejection CMOS low-noise amplifier design optimization techniques

Design and analysis of symmetric dual-layer spiral inductors for RF integrated circuits

A transmitter front-end design for 5GHz WLAN applications

Measured Results on Symmetric Dual-Level Spiral Inductors for RF ICs