We have previously proposed a way of using coupled quantum dots to construct digital computing elements - quantum-dot cellular automata (QCA) Here we consider a different approach to using coupled quantum-dot cells in an architecture which, rather that reproducing Boolean logic, uses a physical near-neighbor connectivity to construct an analog Cellular Neural Network (CNN)

Quantum Cellular Neural Networks

Quantum-dot cellular automaton (QCA) has emerged as one of the best alternatives to CMOS technology in nanoscale. In spite of the potential advantages of QCA technology over CMOS, QCA circuits often suffer from various types of manufacturing defects and are therefore prone to fault. Hence, the design of fault-tolerant circuits in QCA technology is considered a necessity. The implementation of multiplexer circuits in QCA technology has been of great interest to researchers due to its widespread use in memory circuits and ALUs. In most of the multiplexer circuits presented in QCA, the problem of fault-tolerant is ignored. In this paper, a novel fault-tolerant three-input majority gate is initially proposed. The proposed structure has been investigated against all kinds of cell omission, extra cell deposition, and cell displacement defects. The simulation results are verified by QCA Designer 2.0.3, and it showed that it is 100, 84.98, and 100% tolerant to single-cell omission, double-cell omission, and extra cell deposition, respectively. In addition, the proposed structure shows that it is robust against cell displacement defects. Moreover, physical investigations are provided in order to confirm the function of the proposed fault-tolerant structure. Finally, using the proposed structure, a novel single-layer 2:1 multiplexer is presented. The results of comparisons indicate that the proposed designs are more reliable than the existing designs. Furthermore, QCAPro power estimator tool is employed to estimate the energy dissipation of the proposed structure.

A novel fault-tolerant multiplexer in quantum-dot cellular automata technology

Inverter and majority gates are considered as two important primitive gates for designing logical circuits in the quantum-dot cellular automata (QCA) technology. Up to now, many QCA layouts have been introduced for three-input majority gates, most of which are not robust against the QCA defects and so they are prone to faults. In this paper, we propose an efficient fault-tolerant 3-input majority gate with ten simple and rotated cells whose output signal strength is very high (± 9.93e−001). The fault tolerance of the proposed structure is investigated against cell omission, extra-cell deposition, and displacement defects. The results show that the proposed structure is 100% and 90% tolerant against single-cell omission and extra-cell deposition defects. Moreover, the error probability of the proposed gate under cell omission and extra-cell deposition defects is investigated through analytical modeling. Using the proposed fault-tolerant structure, two basic circuits including a fault-tolerant QCA full-adder and a fault-tolerant 2:1 QCA multiplexer are introduced. Finally, using the proposed circuits, a fault-tolerant one-bit arithmetic logic unit with four mathematical and logical operations is designed and implemented. To verify the proposed three-input majority gate, some physical proofs are provided. The results of simulations by QCADesigner 2.0.3 show that the proposed circuits work well. The power analysis of the proposed structure is performed using a QCAPro tool. The comparison results show that the proposed circuits are much better than the previous designs.

The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate

A novel fault tolerant majority gate in quantum-dot cellular automata to create a revolution in design of fault tolerant nanostructures, with physical verification

This brief presents an efficient single-layer serial-parallel multiplier (SPM) in Quantum-dot Cellular Automata (QCA). We have designed a bit-serial adder (BSA) using a fully utilized majority gate (MV), and a modified E-shaped exclusive-OR (E-XOR) gate. The cell-interactive properties of the QCA cell have been utilized to realize the proposed E-XOR gate. This new gate leads the proposed SPM to achieve a reduction in cell count and area by 30% and 19%, 29% and 24%, 30% and 22%, 32% and 39%, and 36% and 46% for 4-, 8-, 16-, 32-, and 64-bit multipliers, respectively. All proposed circuits have been simulated and verified by using QCADesigner with a coherence vector simulation engine. In addition, the average switching and leakage energy dissipation are estimated using QCAPro tool.

Design of QCA-Serial Parallel Multiplier (QSPM) With Energy Dissipation Analysis

Due to its ultrasmall size and extremely low power consumption, quantum-dot cellular automata (QCA) technology represents a promising alternative to semiconductor transistors at the nanoscale. Nevertheless, the design of QCA circuits is limited by their high defect rate during fabrication, making fault-tolerant QCA structures a popular research topic. The aim of this work is to design a new fault-tolerant QCA majority gate based on a $$3\times 5$$3×5 tile. The majority gate guarantees good fault tolerance under single cell and double cell missing defects compared with several previous structures. The functional results when adopting the polarization and kink energy of the proposed majority gate under such single cell and double cell deposition defects are fully investigated. Besides, a series of new fault-tolerant adders are implemented based on the fault-tolerant majority gates. To evaluate the performance of the proposed adders, a thorough comparison versus previous adders with respect to fault tolerance, cell number, area, and delay is carried out. The results indicate that the proposed design can reach a high level of fault tolerance, and perform rather well in terms of other properties. For simulation analysis, the QCADesigner tool is used to check the functionality of all circuits.

Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata

Summary

Quantum-dot cellular automata (QCA) is an emerging technology with the rapid development of low-power high-performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit-serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit-serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

In this paper we propose two quantum secure direct dialogue (QSDD) schemes with logical Bell states which can resist collective noise. The two users Alice and Bob encode their secret messages with the help of unitary operations. Compared with many quantum secure direct communication (QSDC), there is no strict information sender and receiver in these schemes, one logical Bell state can be operated twice by Alice and Bob based on what messages they prefer to encode. As a result, the two users are able to share their messages mutually, so the efficiency of communication is improved. By rearranging the order of particles and inserting decoy photons, our protocols are able to avoid the information leakage and detect eavesdropping, and they can be proved to have unconditional security.

Robust Anti-Collective Noise Quantum Secure Direct Dialogue Using Logical Bell States

This paper presents an all-digital PLL (ADPLL) for the pixel clock regeneration in analog video signal digitization applications. A fine frequency resolution, 1-1-1 MASH structure based fractional-N PLL (FN-PLL) is used as the Digital-Controlled Oscillator (DCO). Two loop filters which are triggered by different clock frequencies and both with adaptive gain controllers are combined together working at different states to increase both the tracking speed and the locked jitter performance. The ADPLL maximum output frequency is determined by the FN-PLL’s voltage-controlled oscillator (VCO) which can be upper than 1Ghz. It covers any VESA and HDTV specification requirements even at 4X over-sampling ratio. A test chip contains this ADPLL prototype has been implemented in a 0.13um CMOS technology. The layout area is about 0.2mm2, the measured RMS jitter is 32.4ps.

Guangjun Xie

Papers

Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Robust Anti-Collective Noise Quantum Secure Direct Dialogue Using Logical Bell States

An All-Digital PLL for Video Pixel Clock Regeneration Applications

Design and implementation of programmable logic array using crossbar structure in quantum-dot cellular automata