This paper presents a 28-GHz CMOS four-element phased-array transceiver chip for the fifth-generation mobile network (5G) new radio (NR). The proposed transceiver is based on the local-oscillator (LO) phase-shifting architecture, and it achieves quasi-continuous phase tuning with less than 0.2-dB radio frequency (RF) gain variation and 0.3°C phase error. Accurate beam control with suppressed sidelobe level during beam steering could be supported by this work. At 28 GHz, a single-element transmitter-mode output ${{\mathrm {P}}_{\mathrm {1\,dB}}}$ of 15.7 dBm and a receiver-mode noise figure (NF) of 4.1 dB are achieved. The eight-element transceiver modules developed in this work are capable of scanning the beam from −50° to +50° with less than −9-dB sidelobe level. A saturated equivalent isotropic radiated power (EIRP) of 39.8 dBm is achieved at 0° scan. In a 5-m over-the-air measurement, the proposed module demonstrates the first 512 quadrature amplitude modulation (QAM) constellation in the 28-GHz band. A data stream of 6.4 Gb/s in 256-QAM could be supported within a beam angle of ±50°. The achieved maximum data rate is 15 Gb/s in 64-QAM. The proposed transceiver chip consumes 1.2 W/chip in transmitter mode and 0.59 W/chip in receiver mode.

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A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

A low-power 28-GHz phased-array receiver (RX) front end is presented that incorporates a low-power low-noise amplifier (LNA) and a passive reflection-type phase shifter (RTPS) capable of 360° phase shift with 5-b phase resolution and low gain variation. Passive phase shifters are limited by tradeoffs between phase resolution, insertion loss, and phase shift range. The proposed RTPS load design and optimization approach leads to a 28-GHz RTPS achieving the state-of-the-art insertion loss with 360° phase shift range and low loss variation across the phase shift. The LNA adopts a transformer-coupled neutralization architecture that increases available gain, enabling lower power consumption. The phased-array front end is designed for Ka -band applications and has been implemented in 65-nm CMOS. The measured RTPS achieves 360° phase shift with 7.75 ± 0.3 dB insertion loss and an rms phase error of 0.3° at 28 GHz. The low-power phased-array RX front end has an overall gain of 9.5 ± 0.4 dB and noise figure <5.5 dB at 28 GHz. The RX front end consumes 10 mW from a 0.9-V supply with phase shifter and an LNA active area of 0.16 and 0.32 mm2, respectively, in 65-nm CMOS, demonstrating its suitability for low-power phased-array RX for emerging wireless links.

A 28-GHz Low-Power Phased-Array Receiver Front-End With 360° RTPS Phase Shift Range

A 6-bit high-accuracy active phase shifter is developed in 0.13- $\mu \text{m}$ CMOS technology for Ku -band phased arrays. Improved transformer balun with wriggly stub is applied to split the single input to differential and achieve high balance with reduced chip area. Two-stage polyphase filter (PPF) generates broadband I/Q signals with high accuracy. A main digital-to-analog convertor (DAC) controls the I/Q amplitude to achieve 6-bit phase resolution, while an auxiliary DAC compensates the amplitude/phase error introduced by balun and PPF. Consequently, high resolution along with low phase/gain error can be achieved. The phase shifter shows measured rms phase error of $0.75 \times 0.32$ mm2 excluding pads.

A 6-bit CMOS Active Phase Shifter for Ku -Band Phased Arrays

This paper presents a 0.53-THz subharmonic injection-locked $1\times 4$ phased array based on an injection-locked oscillator (ILO) chain. Thanks to the ILO chain, the phase errors in the phased array can be compensated without introducing power variation. This technique enables accurate beam steering with a 60° scan range in the $E$ -plane at 0.53 THz. A six-stage triple-push oscillator is proposed to generate the signal at 0.53 THz. Compared with a conventional triple-push oscillator, it reduces layout constraints, improves signal balance, and enhances output power by at least 3 dB. The phased array is implemented in 40-nm CMOS. With an injection power of 0 dBm, the injection-locked phased array generates an output frequency from 529 to 534 GHz. At 531.5 GHz, the proposed phased array achieves −12-dBm radiated power and 0.24‰ dc-to-terahertz (THz) efficiency without the use of silicon lens, quartz superstrate, or substrate thinning. The chip consumes 260-mW dc power and occupies an area of 2.5 mm2.

/pdf/a-0-53-thz-subharmonic-injection-locked-phased-array-with-63-267rbcxtce.pdf

A 0.53-THz Subharmonic Injection-Locked Phased Array With 63- $\mu$ W Radiated Power in 40-nm CMOS

Large-scale millimeter-wave (mm-Wave) integrated phased array is the key technology to enable broadband 5G and satellite communications. This paper details the design considerations, challenges and trade-offs of mm-Wave integrated phased arrays based on bulk CMOS and multi-layer hybrid PCB technologies. Both technologies attain high yield and low cost for mass production. Important beamforming building blocks are addressed and compared in detail. Demonstrators of integrated phased arrays are presented from circuit to board levels. The 1024- and 4096-element integrated phased arrays achieve the EIRP of 72.5 and 84.0 dBm respectively. Finally, relevant phased-array transceivers and antennas from the recent literature are discussed.

Millimeter-Wave Integrated Phased Arrays

This letter presents a 28 GHz low insertion loss and compact size 4-bit phase shifter in 65 nm CMOS Technology. In order to get low insertion loss and compact size, this phase shifter is composed of two types of passive phase shifters, high-pass/low-pass type and switched filter type. Various techniques are used such as triple well body-floating, gate-floating, removal of capacitance of the off-state transistor using resonant inductor, and minimized interconnection line which is based on matching network. This phase shifter has 6.36 dB of average insertion loss over the 27.5–28.35 GHz, and loss variation is about 2 dB. The return loss is higher than 12 dB, RMS phase error is 8.98 $^{\circ}$ , OIP3 is 8.1 dBm at $-$ 10 dBm input power and its core size is 636 $\mu$ m $\times$ 360 $\mu$ m. To the authors' knowledge, these results are the state of the art in CMOS passive phase shifters in K-band frequency.

Gyeong-Seop Shin

Papers

Low Insertion Loss, Compact 4-bit Phase Shifter in 65 nm CMOS for 5G Applications