This paper presents a 28-GHz CMOS four-element phased-array transceiver chip for the fifth-generation mobile network (5G) new radio (NR). The proposed transceiver is based on the local-oscillator (LO) phase-shifting architecture, and it achieves quasi-continuous phase tuning with less than 0.2-dB radio frequency (RF) gain variation and 0.3°C phase error. Accurate beam control with suppressed sidelobe level during beam steering could be supported by this work. At 28 GHz, a single-element transmitter-mode output ${{\mathrm {P}}_{\mathrm {1\,dB}}}$ of 15.7 dBm and a receiver-mode noise figure (NF) of 4.1 dB are achieved. The eight-element transceiver modules developed in this work are capable of scanning the beam from −50° to +50° with less than −9-dB sidelobe level. A saturated equivalent isotropic radiated power (EIRP) of 39.8 dBm is achieved at 0° scan. In a 5-m over-the-air measurement, the proposed module demonstrates the first 512 quadrature amplitude modulation (QAM) constellation in the 28-GHz band. A data stream of 6.4 Gb/s in 256-QAM could be supported within a beam angle of ±50°. The achieved maximum data rate is 15 Gb/s in 64-QAM. The proposed transceiver chip consumes 1.2 W/chip in transmitter mode and 0.59 W/chip in receiver mode.

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A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

A low-power 28-GHz phased-array receiver (RX) front end is presented that incorporates a low-power low-noise amplifier (LNA) and a passive reflection-type phase shifter (RTPS) capable of 360° phase shift with 5-b phase resolution and low gain variation. Passive phase shifters are limited by tradeoffs between phase resolution, insertion loss, and phase shift range. The proposed RTPS load design and optimization approach leads to a 28-GHz RTPS achieving the state-of-the-art insertion loss with 360° phase shift range and low loss variation across the phase shift. The LNA adopts a transformer-coupled neutralization architecture that increases available gain, enabling lower power consumption. The phased-array front end is designed for Ka -band applications and has been implemented in 65-nm CMOS. The measured RTPS achieves 360° phase shift with 7.75 ± 0.3 dB insertion loss and an rms phase error of 0.3° at 28 GHz. The low-power phased-array RX front end has an overall gain of 9.5 ± 0.4 dB and noise figure <5.5 dB at 28 GHz. The RX front end consumes 10 mW from a 0.9-V supply with phase shifter and an LNA active area of 0.16 and 0.32 mm2, respectively, in 65-nm CMOS, demonstrating its suitability for low-power phased-array RX for emerging wireless links.

A 28-GHz Low-Power Phased-Array Receiver Front-End With 360° RTPS Phase Shift Range

This paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3- to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of −106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of −184 dBc/Hz at 27.3 GHz. Its flicker phase-noise ( $1/f^{3}$ ) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

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A Low-Flicker-Noise 30-GHz Class-F 23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path

This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its phase noise analysis, optimization, and design for future 5G wireless transceivers. The performance improvement of the cascaded phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption is theoretically presented and verified with measured results. The cascaded PLL is implemented using a first-stage fractional-N charge-pump PLL followed by a second-stage quadrature dividerless subsampling PLL. The fractional division in the first-stage PLL is implemented using a high-resolution phase mixer for lower quantization noise. Two prototypes of the single-stage PLL and the cascaded PLL were implemented in the 65-nm bulk CMOS process. The 26–32 GHz quadrature cascaded PLL consumes a total of 26.9 mW from 1-V supply and achieves less than 100-fs integrated jitter with −116.2 and −112.6-dBc/Hz phase noise at 1-MHz offset for the integer-N and the fractional-N modes, respectively. The fractional-N single-stage and cascaded PLLs achieve figure-of-merits of −230.58 and −248.75 dB, respectively.

A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture

A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-antenna transceivers is presented. The system is modular with one phase locked loop (PLL) per antenna element transceiver, and a test circuit implemented in 28-nm fully depleted silicon on insulator (FD-SOI) CMOS features two such PLLs and a 491.52 MHz crystal oscillator (XO) generating a common frequency reference. A fractional-N architecture is employed to achieve high-frequency resolution, and the quantization noise is reduced using a novel frequency divider, which achieves full integer resolution while still using a pre-scaler. The system covers the 3rd Generation Partnership Project (3GPP) bands n257 and n258, achieved by a digital coarse tuning of the voltage-controlled oscillator (VCO). The chip area of each PLL is 0.11 mm2, and 0.029 mm2 for the XO. The total power consumption of the system is 35 mW, where each PLL consumes 15.4 mW and the XO consumes 0.84 mW. The total rms jitter from 20-kHz to 500-MHz offset for a 26-GHz carrier is just 115 fs, corresponding to an FOM $_{\vphantom {R_{j}}j}$ of −244 dB, which is the best reported figure for a fractional-N PLL above 15 GHz. The error-vector magnitude (EVM) due to phase noise is −34.6 dBc using an orthogonal frequency-division multiplexing (OFDM) signal with 120-kHz sub-carrier spacing, sufficient to support 256 QAM.

A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24–30-GHz Sliding-IF 5G Transceivers

This letter presents a 28 GHz low insertion loss and compact size 4-bit phase shifter in 65 nm CMOS Technology. In order to get low insertion loss and compact size, this phase shifter is composed of two types of passive phase shifters, high-pass/low-pass type and switched filter type. Various techniques are used such as triple well body-floating, gate-floating, removal of capacitance of the off-state transistor using resonant inductor, and minimized interconnection line which is based on matching network. This phase shifter has 6.36 dB of average insertion loss over the 27.5–28.35 GHz, and loss variation is about 2 dB. The return loss is higher than 12 dB, RMS phase error is 8.98 $^{\circ}$ , OIP3 is 8.1 dBm at $-$ 10 dBm input power and its core size is 636 $\mu$ m $\times$ 360 $\mu$ m. To the authors' knowledge, these results are the state of the art in CMOS passive phase shifters in K-band frequency.

Low Insertion Loss, Compact 4-bit Phase Shifter in 65 nm CMOS for 5G Applications

This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing noise-folding effect resulting low in-band phase noise while sampling loop filter helps reducing spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively while consuming only 33mW. The jitter-power figure-of-merit (FoM) is -231dB which is the highest among the state-of-the-art >20GHz fractional-N PLLs. Reference spurs are less than -80 dBc.

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular

A CMOS millimeter-wave (mmWave) downconversion mixer with a local-oscillator (LO) buffer is proposed for wireless Gb/s data-transfer enabling systems, such as 5G systems. To obtain high linearity at low supply voltages, the proposed mmWave downconversion mixer adopts an on-chip transformer-based topology. In order to achieve differential to single-ended conversion and IF output matching, while maintaining a high linearity performance, the proposed mmWave downconversion mixer incorporates an active balun with common-source and common-drain configurations employing common-mode noise and third-order intermodulation distortion cancellations. The proposed downconversion mixer with active balun and LO buffer was implemented using a 65-nm CMOS process and it draws 18 mA from a 1 V supply voltage. It demonstrates a gain greater than 5.6 dB, noise figure less than 10.9 dB, and third-order output intercept point more than 12.4 dBm, in the band from 57 to 66 GHz.

A +12-dBm OIP3 60-GHz RF Downconversion Mixer With an Output-Matching, Noise- and Distortion-Canceling Active Balun for 5G Applications

This paper presents a method to design Wilkinson power divider using transmission lines less than quarter wave length. The transmission lines less than quarter wave length of Wilkinson power divider is compensated by parallel capacitors. Therefore, this is helpful to reduce circuit size and to enhance productivity. The measurement results reveal that the insertion loss is 0.82 dB at 28 GHz. The measured return loss is better than 10 dB in the whole band of interest (20–40 GHz). The Wilkinson power divider is fabricated using 65 nm 1P9M CMOS technology.

28 GHz Wilkinson power divider with λ/6 transmission lines in 65nm CMOS technology

A high linearity, high image/LO-rejection in-phase/quadrature (I/Q) direct up-conversion mixer for 5G cellular communications is designed and implemented in 65nm CMOS. The proposed chip is implemented with quadrature LO generator and LO buffer amplifiers, and employs a complementary derivative superposition (DS) technique with pre-distortion for high linearity. The symmetric layout enhances the image/LO-rejection. The proposed mixer achieves the output 1-dB compression point of 2dBm and output third-order intercept point of 15.7dBm at 27.6GHz while consumes 15mW from 1V power supply. The measured conversion gain is 11.4dB and the measured image rejection ratio and LO leakage are −61dBc and −56dBc, respectively.

Ju Ho Son

Papers

Low Insertion Loss, Compact 4-bit Phase Shifter in 65 nm CMOS for 5G Applications

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular

A +12-dBm OIP3 60-GHz RF Downconversion Mixer With an Output-Matching, Noise- and Distortion-Canceling Active Balun for 5G Applications

28 GHz Wilkinson power divider with λ/6 transmission lines in 65nm CMOS technology

A high linearity, image/LO-rejection I/Q up-conversion mixer for 5G cellular communications