In this paper we present theory and experiments on the algebraic decision diagrams (ADDs). These diagrams extend BDD's by allowing values from an arbitrary finite domain to be associated with the terminal nodes. We present a treatment founded in Boolean algebras and discuss algorithms and results in applications like matrix multiplication and shortest path algorithms. Furthermore, we outline possible applications of ADD's to logic synthesis, formal verification, and testing of digital systems.

Algebraic decision diagrams and their applications

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is modified to represent state graphs using binary decision diagrams (BDD's) and partitioned transition relations. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5/spl times/10/sup 120/ states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to express a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic. >

Symbolic model checking for sequential circuit verification

Clustered voltage scaling technique for low-power design

We survey several results and open problems related to synchronizing automata. In particular, we discuss some recent advances towards a solution of the Cerný conjecture.

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Synchronizing Automata and the Černý Conjecture

We present a robust, efficient algorithm for combinational test generation using a reduction to satisfiability (SAT) The algorithm, Test Generation Using Satisfiability (TEGUS), solves a simplified test set characteristic equation using straightforward but powerful greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point For difficult faults, the computation of global implications is iterated, which finds more implications than previous approaches and subsumes structural heuristics such as unique sensitization Without random tests or fault simulation, TEGUS completes on every fault in the ISCAS networks, demonstrating its robustness, and is ten times faster for those networks which have been completed by previous algorithms Our implementation of TEGUS can be used as a base line for comparing test generation algorithms; we present comparisons with 45 recently published algorithms TEGUS combines the advantages of the elegant organization of SAT-based algorithms with the efficiency of structural algorithms

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Combinational test generation using satisfiability

Finite state machine (FSM) verification based on implicit state enumeration can be extended to test generation and redundancy identification. The extended method constructs the product machine of two FSMs to be compared, and reachability analysis is performed by traversing the product machine to find any difference in I/O behavior. When an output difference is detected, the information obtained by reachability analysis is used to generate a test sequence. This method is complete, and it generates one of the shortest possible test sequences for a given fault. However, applying this method indiscriminately for all faults may result in unnecessary waste of computer resources. An efficient method based on reachability analysis of the fault-free machine (three-phase ATPG) in addition to the powerful but more resource-demanding product machine traversal is presented. The application of these algorithms to the problems of generating test sequences, identifying redundancies, and removing redundancies is reported. >

Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration

Algorithms are presented for finite state machine (FSM) verification and image computation which improve on the results of O. Coudert et al (1989), giving 1-4 orders of magnitude speedup. Novel features include primary input splitting-this PODEM feature enlarges the search space but shortens the search due to implications. Another new feature, identical subtree recombination, is shown to be effective for iterative networks (eg, serial multipliers). The free-variable recognition feature prevents unbalanced bipartitioning trees in tautological subspaces. Finally, reached set pruning is significant when the image contains large numbers of previously reached states. >

ATPG aspects of FSM verification

In this paper we present algorithms for approximate FSM traversal based on state space decomposition. The original FSM is partitioned in sub-machines, and each of them is traversed separately; the result is an over-estimation of the set of reachable states. Several traversal strategies are discussed. Good partitioning is important for the performance of the traversal techniques; a method to heuristically find an appropriate decomposition, based on the exploration of the FSM latch connection graph, is proposed. Applications of the approximate traversal methods to sequential optimization and behavioral verification of FSM's are described; experimental results for such applications, together with data concerning pure traversal, are reported.

Algorithms for Approximate FSM Traversal

This paper presents algorithms for approximate finite state machine traversal based on state space decomposition. The original finite state machine is partitioned in component submachines, and each of them is traversed separately; the result of the computation is an over-estimation of the set of reachable states of the original machine. Different traversal strategies, which reduce the effects of the degrees of freedom introduced by the decomposition, are discussed. Efficient partitioning is a key point for the performance of the traversal techniques; a method to heuristically find a good decomposition of the overall finite state machine, based on the exploration of its state variable dependency graph, is proposed. Applications of the approximate traversal methods to logic optimization of sequential circuits and behavioral verification of finite state machines are described; experimental results for such applications, together with data concerning pure traversal, are reported.

Algorithms for approximate FSM traversal based on state space decomposition

Asynchronizing sequence drives a circuit from an arbitrary power-up state into a unique state. Test generation on a circuit without a reset state can be much simplified if the circuit has a synchronizing sequence. In this article, a framework and algorithms for test generation based on themultiple observation time strategy are developed by taking advantage of synchronizing sequences. Though it has been shown that the multiple observation time strategy can provide a higher fault coverage than the conventional single observation time strategy, until now the multiple observation time strategy has required a very complex tester operation model (referred asMultiple Observation time-Multiple Reference strategy (MOMR) in the sequel) over the conventional tester operation model. The overhead of MOMR, exponential in the worst case, has prevented widespread use of the method. However, when a circuit is synchronizable, test generation can employ the multiple observation time strategy and provide better fault coverages, without resorting to MOMR. This testing strategy is referred asMultiple Observation time-Single Reference strategy (MOSR). We prove in this article that the same fault coverage, that could be achieved in MOMR, can be obtained in MOSR, if the circuit under test generation is synchronizable. We investigate how a synchronizing sequences simplifies test generation and allows to use MOSR under multiple observation time strategy. The experimental results show that higher fault coverages and large savings in CPU time can be achieved by the proposed framework and algorithms over both existing single observation time strategy methods as well as other multiple observation time strategy methods.

H. Cho

Papers

Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration

ATPG aspects of FSM verification

Algorithms for Approximate FSM Traversal

Algorithms for approximate FSM traversal based on state space decomposition

Synchronizing sequences and symbolic traversal techniques in test generation