Proceedings ArticleDOI
ATPG aspects of FSM verification
H. Cho,Gary D. Hachtel,Seh-Woong Jeong,B. Plessier,Eric M. Schwarz,Fabio Somenzi +5 more
- pp 134-137
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TLDR
Algorithms are presented for finite state machine (FSM) verification and image computation which improve on the results of O. Coudert et al (1989), giving 1-4 orders of magnitude speedup.Abstract:Â
Algorithms are presented for finite state machine (FSM) verification and image computation which improve on the results of O. Coudert et al (1989), giving 1-4 orders of magnitude speedup. Novel features include primary input splitting-this PODEM feature enlarges the search space but shortens the search due to implications. Another new feature, identical subtree recombination, is shown to be effective for iterative networks (eg, serial multipliers). The free-variable recognition feature prevents unbalanced bipartitioning trees in tautological subspaces. Finally, reached set pruning is significant when the image contains large numbers of previously reached states. >read more
Citations
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Proceedings ArticleDOI
Algebraic decision diagrams and their applications
R. Iris Bahar,Erica A. Frohm,Charles M. Gaona,Gary D. Hachtel,Enrico Macii,Abelardo Pardo,Fabio Somenzi +6 more
TL;DR: This paper presents a treatment founded in Boolean algebras and discusses algorithms and results in applications like matrix multiplication and shortest path algorithms, and outlines possible applications of ADD's to logic synthesis, formal verification, and testing of digital systems.
Journal ArticleDOI
Symbolic model checking for sequential circuit verification
TL;DR: In this paper, the temporal logic model checking algorithm of Clarke, Emerson, and Sistla is modified to represent state graphs using binary decision diagrams (BDD's) and partitioned transition relations.
Book ChapterDOI
A unified framework for the formal verification of sequential circuits
TL;DR: A unified framework for the verification of synchronous circuits is presented and two verification tasks, verification by actual execution and by simulation, can be automatically performed using algorithms based on the same concepts.
Journal ArticleDOI
Algebric Decision Diagrams and Their Applications
R.I. Bahar,E. A. Frohm,C. M. Gaona,Gary D. Hachtel,Enrico Macii,Abelardo Pardo,Fabio Somenzi +6 more
TL;DR: A treatment founded in Boolean algebras is presented and algorithms and results in several areas of application are discussed: Matrix multiplication, shortest path algorithms, and direct methods for numerical linear algebra.
Journal ArticleDOI
Automatic generation of functional vectors using the extended finite state machine model
TL;DR: Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flip-flops can be generated automatically in a few minutes of CPU time using the prototype system.
References
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Proceedings ArticleDOI
Combinational profiles of sequential benchmark circuits
F. Brglez,D. Bryan,K. Kozminski +2 more
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Proceedings ArticleDOI
Efficient implementation of a BDD package
TL;DR: A package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation is described, based on an efficient implementation of the if-then-else (ITE) operator.
Journal ArticleDOI
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Journal ArticleDOI
Test generation for sequential circuits
TL;DR: The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits.
Proceedings ArticleDOI
Test generation for highly sequential circuits
TL;DR: The authors present a novel test procedure that exploits both the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit, and describe fast algorithms for state justification and state differentiation using the ON sets and OFF sets of flip-flop inputs and primary outputs.