Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

The drift region properties of 6H- and 3C-SiC-based Schottky rectifiers and power MOSFETs that result in breakdown voltages from 50 to 5000 V are defined. Using these values, the output characteristics of the devices are calculated and compared with those of Si devices. It is found that due to very low drift region resistance, 5000-V SiC Schottky rectifiers and power MOSFETs can deliver on-state current density of 100 A/cm/sup 2/ at room temperature with a forward drop of only 3.85 and 2.95 V, respectively. Both devices are expected to have excellent switching characteristics and ruggedness due to the absence of minority-carrier injection. A thermal analysis shows that 5000-V, 6H-, and 3C-SiC MOSFETs and Schottky rectifiers would be approximately 20 and 18 times smaller than corresponding Si devices, and that operation at higher temperatures and at higher breakdown voltages than conventional Si devices is possible. Also, a significant reduction in the die size is expected. >

Comparison of 6H-SiC, 3C-SiC, and Si for power devices

An improved method is presented for calculating the ionization rates αn and αp from charge multiplication measurements on diffused silicon p-n junctions. The main features of this method are: The real impurity profile is approximated by an exponential function whose parameters are calculated from capacitance measurements; the ratio γ = αp/αn as a function of the electric field is calculated from multiplication measurements; the ionization rates are solved from the ionization integral for pure electron injection, taking the influence of the threshold energy into account. Measurements on narrow junctions agree with measurements on wide junctions by assuming a threshold energy of 1.8 eV for electrons, in agreement with the results of M oll and van O verstraeten .(1) The ionization rates differ from those of M oll and van O verstraeten (1) and of L ee , L ogan et al.(2) mainly because these authors neglect the influence of the threshold energy. The electron and hole data satisfy Chynoweth's law α(E) = α ∞ exp (−b/¦E¦), cm −1 with: for electrons α∞ = 7.03 × 105 cm−1 b = 1.231 × 106 V cm−1 for 1.75 × 105 ⩽ E ⩽ 6.0 × 105 V cm−1 for holes α∞ = 1.582 × 106 cm−1b = 2.036 × 106 V cm−1 for 1.75 × 105 ⩽ E ⩽ 4.0 × 105 V cm−1 and α∞ = 6.71 × 105 cm−1b = 1.693 × 106 V cm−1 for 4.0 × 105 ⩽ E ⩽ 6.0 × 105 V cm−1 Breakdown voltages are computed for high voltage p-n and p-i-n diodes. These are in good agreement with experiments, indicating the reliability of the ionization rates.

Measurement of the ionization rates in diffused silicon p-n junctions

A new theory of semiconductor devices, called "semiconductor superjunction (SJ) theory", is presented. To overcome the trade-off relationship between breakdown voltage and on-resistance of conventional semiconductor devices, SJ devices utilize a number of alternately stacked, p- and n-type, heavily doped, thin semiconductor layers. By controlling the degree of doping and the thickness of these layers, according to the SJ theory, this structure operates as a pn junction with low on-resistance and high breakdown voltage. Analytical formulas for the ideal specific on-resistance and the ideal breakdown voltage of SJ devices are theoretically derived. Analysis based on the formulas and device simulations reveals that the on-resistance of SJ devices can be reduced to less than 10-2 that of conventional devices.

https://iopscience.iop.org/article/10.1143/JJAP.36.6254/pdf

Theory of Semiconductor Superjunction Devices

Monte Carlo simulations of electron transport in seven semiconductors of the diamond and zinc-blende structure (Ge, Si, GaAs, InP, AlAs, InAs, GaP) and some of their alloys (Al/sub x/Ga/sub 1-x/As, In/sub x/Ga/sub 1-x/As, Ga/sub x/In/sub 1-x/P) and hole transport in Si were performed at two lattice temperatures (77 and 300 K). The model uses band structures obtained from local empirical pseudopotential calculations and particle-lattice scattering rates computed from the Fermi golden rule to account for band-structure effects. Intervalley deformation potentials significantly lower than those which have been previously reported are needed to reproduce available experimental data. This is attributed to the more complicated band structures, particularly around the L- and X-symmetry points in most materials. Satisfactory agreement is obtained between Monte Carlo results and some experiments. >

Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures. I. Homogeneous transport

A graphical method is presented, which allows the determination, for a p - n junction, of the breakdown voltage and also the electric field distribution, the width of the depletion layer and the multiplication factor, all at a given reverse voltage. This method is based on the approximation of the exact impurity profile by an exponential function. The use of reduced parameters makes the method independent of the material. Numerical examples are presented.

Graphical method for the determination of junction parameters and of multiplication parameters

The gain–bandwidth product fT of a bipolar transistor is calculated, taking the heavy doping effect in the emitter into account. This effect reduces fT, owing to a larger charge storage in the emitter neutral region and a decrease of the built-in voltage of the emitter-base depletion capacitance.

H. de Man

Papers

Measurement of the ionization rates in diffused silicon p-n junctions

Graphical method for the determination of junction parameters and of multiplication parameters

Influence of heavy doping effects on the fT prediction of transistors