This paper presents a CMOS implementation of a low-voltage micropower G/sub m/-C biquad with on-chip automatic tuning. The filter is suitable for any kind of application involving low-frequency ranges, and very low-power consumption, such as biomedical devices. The operational transconductance amplifier (OTA) is implemented with the transistors working in the weak inversion saturation region, thus allowing the use of very small currents that minimize the power consumption. The aspect ratios are small enough not to degrade the frequency response. The tuning algorithm is based on amplitude tracking. The filter output amplitude is quantized using a low-power amplifier and an asymmetric comparator. A digital controller varies the tuning parameters until the maximum quantized amplitude is found. The system works down to a voltage supply of 1.75 V. The center frequency is tunable over one and a half decades, from 300 Hz to 10 kHz for bias currents changing from 6 to 200 nA and a 20-pF integrating capacitance, giving an overall filter accuracy of up to 99.55%. The power consumption of the second-order filter including the common-mode correction circuitry is in the order of 200 nW for the 10-nA bias current. It exhibits a dynamic range of 54 dB and occupies an area of 0.06 mm/sup 2/ excluding the area of the integrating capacitances.

A micropower CMOS continuous-time filter with on-chip automatic tuning

A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency The amplitude of the magnitude responses (409 and 411 ) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits 10 (253 and 254) while the filter is sequenced through a plurality of capacitance settings An optimal capacitance for the R/C circuit is selected by comparing, to a pre¬ selected value, a difference between the responses of the filter to each tone, for each capacitance setting.

Controlling the bandwidth of an analog filter

This paper presents a new RF notch filter topology for image rejection in heterodyne receivers. The circuit is combined with a cascode low noise amplifier (LNA) and an output buffer for testing purposes. It is implemented with standard CMOS 0.18/spl mu/m technology. The notch filter is tunable from 10.5 to 11.1GHz. Up to 10dB controllable gain is obtained from the LNA in the pass band at 6.5GHz. A -50dB image rejection is realized by using on chip inductor Q-factor enhancement techniques. At the maximum in band gain of 12dB and -50dB image rejection, the circuit consumes 22mW of power with a noise figure of 2.4dB, a -12.5dB IIP3, from a 1.5V power supply.

A 1.5V multigigahertz CMOS tunable image reject notch filter

A method for tuning quality factor (Q) in a high-Q, high-frequency filter is provided that includes filtering an input signal to generate a filtered signal. The input signal comprises a specified frequency. The filtered signal comprises an actual phase shift with respect to the input signal. The actual phase shift is compared to a desired phase shift for the filtered signal to determine a difference between the actual phase shift and the desired phase shift. The desired phase shift corresponds to the specified frequency. The filter is tuned based on the difference between the actual phase shift and the desired phase shift.

Method and system for tuning quality factor in high-Q, high-frequency filters

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A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme

A fourth-order CMOS transconductance-C (Gm-C) bandpass filter with on-chip automatic frequency tuning for wireless receiver filtering applications is proposed. A linearized transconductance (Gm) cell is designed and optimized for phase error cancellation. The center frequency of the filter is locked to an external reference frequency using an Adaptive Gain Phase-Locked Loop (AGPLL). The purpose of the AGPLL technique is to provide a short locking time which is under 50 clock cycles, it decreases the filter time response. The power supply of the proposed design is 2.2 volts and the whole circuit has been implemented in 0.35 um CMOS technology available through the Canadian Microelectronics Corporation (CMC).

High frequency CMOS Gm-C bandpass filter with automatic on-chip tuning

A maximally flat magnitude 70 MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented The input equivalent noise is 19 /spl mu/V/sqr(Hz) which shows that the nonlinearity at the input of the filter is very small The IIP3 (the input level of the third-order intercept point) of the filter is -925dBm The complete system operates with a supply voltage of 22 V All this has been achieved due to the use of a low distortion transconductor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control The whole circuit has been implemented in 035 /spl mu/m CMOS technology available through the Canadian Microelectronics Corporation (CMC)

H. Elhallabi

Papers

High frequency CMOS Gm-C bandpass filter with automatic on-chip tuning

High frequency and high Q CMOS GM-C bandpass filter with automatic on-chip tuning