This paper presents a CMOS implementation of a low-voltage micropower G/sub m/-C biquad with on-chip automatic tuning. The filter is suitable for any kind of application involving low-frequency ranges, and very low-power consumption, such as biomedical devices. The operational transconductance amplifier (OTA) is implemented with the transistors working in the weak inversion saturation region, thus allowing the use of very small currents that minimize the power consumption. The aspect ratios are small enough not to degrade the frequency response. The tuning algorithm is based on amplitude tracking. The filter output amplitude is quantized using a low-power amplifier and an asymmetric comparator. A digital controller varies the tuning parameters until the maximum quantized amplitude is found. The system works down to a voltage supply of 1.75 V. The center frequency is tunable over one and a half decades, from 300 Hz to 10 kHz for bias currents changing from 6 to 200 nA and a 20-pF integrating capacitance, giving an overall filter accuracy of up to 99.55%. The power consumption of the second-order filter including the common-mode correction circuitry is in the order of 200 nW for the 10-nA bias current. It exhibits a dynamic range of 54 dB and occupies an area of 0.06 mm/sup 2/ excluding the area of the integrating capacitances.

A micropower CMOS continuous-time filter with on-chip automatic tuning

In this paper we describe a novel PLL circuit design. The proposed topology is based on two loops: the conventional fine loop and a new coarse loop. The fine tuning loop which includes a phase-frequency detector, a charge pump and a differential voltage controlled oscillator (unity feedback PLL) is rather slow. However the coarse tuning loop reacts faster and accelerates convergence. It also ensures a better stability, a shorter locking time, and as a result, a low jitter is obtained, as well as a lower sensitivity to power supply variations.

A new fully integrated CMOS phase-locked loop with low jitter and fast lock time

The rapid growth in the network-communication-system market has placed higher demands on radio-frequency (RF) transceivers. The voltage-controlled oscillator (VCO) is one of the most important building blocks of any communications system, and a high-performance VCO is critical to cover new requirements in communication systems such as required frequency bandwidth recommended by ITU-R, high phase noise performance, power consumption, die size and its cost.

Performance Review of High-Quality-Factor, Low-Noise, and Wideband Radio-Frequency LC-VCO for Wireless Communication [Application Notes]

Phase-locked loop (PLL) fast lock circuit and method using a second frequency controlled feedback loop to complement a primary frequency and phase controlled feedback loop. The second loop may charge a capacitor controlling input voltage to a voltage controlled oscillator (VCO) up and down faster that the primary loop, such as using up and a down charge pumps. In some cases, the second loop uses a frequency detector to detect a difference between a reference and feedback signal frequencies; and in response uses logic to control two pump up and two pump down charge pumps. The frequency detector may be configured to receive a reset signal and a lock signal. The reset signal causes the second loop to send a strong pump up charge to the capacitor without waiting for a difference in the frequencies. The lock signal causes the frequency detector to stops counting the difference in the frequencies.

Phase-locked loop fast lock circuit and method

A symmetrical range controller for phase-locked loop circuits includes a first counter coupled to a first signal line, where the first counter is configured to count state transition edges of the first signal, inhibit logic coupled to the first counter, where the inhibit logic is configured to inhibit an output signal of a second counter in response to a predetermined count of the first counter, and reset logic coupled to the first counter, where the reset logic is configured to reset the second counter in response to a full count of the first counter.

Symmetrical range controller circuit and method

Presents a fully integrated CMOS fast phase locked loop (PLL), based on a new wide swing differential voltage controlled oscillator (WSDVCO). The proposed PLL incorporates new simple architecture of well known PLL building blocks (a dynamic phase-frequency detector, a charge pump, an on-chip low-pass filter, a WSDVCO and a frequency divider). The present version of the WSDVCO allows one to obtain wide tuning range of 40 to 730 MHz simulated with Spectre simulator using 0.25 /spl mu/m CMOS technology. The simplicity of the proposed PLL building blocks permits one to design high performance PLL.

CMOS wide-swing differential VCO for fully integrated fast PLL

In this paper, we describe a novel PLL circuit design with a variable control gain technique. The proposed PLL includes a Phase-Frequency Detector (PFD), a Variable Controlled Gain Charge Pump (VCGCP) based on a frequency detector and a Frequency-to-Voltage Converter (FVC), a Differential Voltage Controlled Oscillator (DVCO) and a frequency divider. First, the PLL reacts quickly and accelerates convergence using the high gain charge pump, then when the frequency deviation decreases, then the VCGCP changes the gain in the same drift. It also ensures a better stability, a shorter locking time, and as a result, a low jitter is obtained. Two PLL circuits were simulated under the same conditions: the first one uses VCGCP technique and locks after 560 ns, while the second classical PLL locks after 5 /spl mu/s.

Very short locking time PLL based on controlled gain technique

A fourth-order CMOS transconductance-C (Gm-C) bandpass filter with on-chip automatic frequency tuning for wireless receiver filtering applications is proposed. A linearized transconductance (Gm) cell is designed and optimized for phase error cancellation. The center frequency of the filter is locked to an external reference frequency using an Adaptive Gain Phase-Locked Loop (AGPLL). The purpose of the AGPLL technique is to provide a short locking time which is under 50 clock cycles, it decreases the filter time response. The power supply of the proposed design is 2.2 volts and the whole circuit has been implemented in 0.35 um CMOS technology available through the Canadian Microelectronics Corporation (CMC).

High frequency CMOS Gm-C bandpass filter with automatic on-chip tuning

A fully integrated Phase Locked Loop (PLL) with wide lock range is presented in this paper. The designed structure of the PLL is based on the charge-pump type with a differential architecture Voltage Controlled Oscillator (VCO) building block. In the proposed VCO, current mirrors are used as the active load of the source-followers which allow a high stability of VCO oscillation within a wide control range. The PLL has been implemented in 0.8 /spl mu/m BiCMOS technology without the need of any external components. It operates with a lock range of 14 to 420 MHz. The lock time is 15 /spl mu/S. The resulting layout area and the power dissipation of the whole PLL are 0.65 mm/sup 2/ and 18 mW respectively.

https://ieeexplore.ieee.org/iel5/6666/17816/00825617.pdf

Y. Fouzar

Papers

A new fully integrated CMOS phase-locked loop with low jitter and fast lock time

CMOS wide-swing differential VCO for fully integrated fast PLL

Very short locking time PLL based on controlled gain technique

High frequency CMOS Gm-C bandpass filter with automatic on-chip tuning

A BiCMOS wide-lock range fully integrated PLL