The performance potential and scaling characteristics of thin-base SOI symmetric lateral bipolar transistors were examined using 1-D analytic equations for the currents and capacitances. The device can operate at collector current densities >100 mA/μm2, and it scales similarly to CMOS in terms of density. The physical base width is scalable to less than 20 nm. Multiple devices of different specifications can be integrated on a chip. A sample design is shown to have fT > 200 GHz, fmax >1 THz, VA > 4V, and a self gain of 60. A balanced design is shown to have 350-GHz fT and 700-GHz fmax, VA of 2.4 V, and a self gain of 20. These results are superior to those reported for 32 nm SOI CMOS. The results suggest a need to rethink bipolar circuit design. They also suggest opportunities for novel bipolar and BiCMOS circuits. The devices in high-speed Si-base bipolar circuits operate at about 1.0 V. The path toward 0.5 V bipolar circuits is to use semiconductors with smaller bandgap, such as Ge.

On the Performance and Scaling of Symmetric Lateral Bipolar Transistors on SOI

A novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically for high packing density and low power-delay product. The basic logic element is a multi-input, multi-output gate, formed in a single-base land by using several diffused collectors and several Schottky base contacts. The lateral p-n-p injector of conventional I/SUP 2/L has been replaced by a vertical arrangement. Factors affecting packing density and power-delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. A preliminary process to demonstrate the feasibility of the vertical injector is described and the measured transistor parameters and power-delay product are given. Experiments to determine suitable conditions for the formation of Schottky barrier diodes are presented, and satisfactory performance for the complete process is demonstrated.

Substrate fed logic

A self-aligned I2L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aligned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-µm design rules and fabricated with this technology exhibit gate delays as small as 0.8 ns at I_{c} = 100 µA for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.

Subnanosecond self-aligned I 2 L/MTL circuits

Schottky I/SUP 2/L uses the principles of integrated injection logic (I/SUP 2/L/MTL) and the properties of ion implantation to obtain improved performance at the same densities as conventional I/SUP 2/L. Schottky diodes are formed in the multicollectors of the switching transistor and reduce the signal swing, thus improving the power delay efficiency. An increase in the intrinsic speed limit is also feasible. The Schottky I/SUP 2/L structure and characteristics are described and contrasted with conventional I/SUP 2/L. A model which is useful for its design is discussed. Integrated test structures which provide direct comparison between conventional and Schottky I/SUP 2/L performance have been fabricated. The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/SUP 2/L over conventional I/SUP 2/L.

Schottky I/sup 2/L

High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.

High speed integrated injection logic (I/sup 2/L)

A simple device model is derived to represent merged transistor logic (MTL) circuit behavior. Using the Ebers-Moll equations, the proper definitions of the various current gains are derived, and it is shown that MTL devices can be basically interpreted as n-p-n transistors having an additional base current source. The relations between the intensity of this source and the current actually supplied are derived. Time behavior is modeled according to the charge control concept. Using this model, circuit delays are given as a function of current gains, collector and emitter time constants, supply current, and of fan-out.

H.H. Berger

Papers

Terminal-oriented model for merged transistor logic (MTL)