This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic elements. A complete charge-based model of the intrinsic part is presented. The main advantage of this new charge-based model is to provide a simple and coherent description of the DC, AC, nonquasi-static (NQS), and noise behavior of the intrinsic MOS that is valid in all regions of operation. It is based on the forward and reverse charges q/sub f/ and q/sub r/ defined as the mobile charge densities, evaluated at the source and at the drain. This intrinsic model also includes a new simplified NQS model that uses a bias and frequency normalization allowing one to describe the high-order frequency behavior with only two simple functions. The extrinsic model includes all the terminal access series resistances, and particularly the gate resistance, the overlap, and junction capacitances as well as a substrate network. The latter is required to account for the signal coupling occurring at RF from the drain to the source and the bulk, through the junction capacitances. The noise model is then presented, including the effect of the substrate resistances on the RF noise parameters. All the aspects of the model are validated for a 0.25-/spl mu/m CMOS process.

An MOS transistor model for RF IC design valid in all regions of operation

An extraction method to obtain the induced gate noise (i~/sub g/~/sup 2/~) channel noise (i~/sub d/~/sup 2/~), and their cross correlation (i~/sub g/~i~/sub d/~*~) in submicron MOSFETs directly from scattering and RF noise measurements has been presented and verified by measurements. In addition, the extracted induced gate noise, channel noise, and their correlation in MOSFETs fabricated in 0.18-/spl mu/m CMOS process versus frequencies, bias conditions, and channel lengths are presented and discussed.

Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFETs from RF noise measurements

Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and small-signal equivalent circuit of the MOSFET, three intrinsic noise parameters (/spl gamma/, /spl delta/, and c) for the drain noise and induced gate noise are calculated. Validity and error analysis for the simulation are discussed by comparing the simulation results with theoretical results as well as measured data.

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

The paper presents a review on physics-based noise simulation techniques for RF semiconductor devices, starting with the small-signal case but with greater stress on noise in large-signal (quasi)-periodic operation. The nonautonomous (forced) operation case will be considered, which is relevant to all RF applications apart from oscillators. Besides their importance in device design, physics-based noise models can also suggest viable and correct strategies to implement circuit-oriented models, e.g., compact models. From this standpoint, the connection between physics-based and circuit-oriented modeling is discussed both in the small-signal and in the large-signal case, with particular stress on the treatment of colored noise in the large-signal periodic regime.

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Physics-based simulation techniques for small- and large-signal device noise analysis in RF applications

T HE IMPORTANCE OF CMOS TECHNOLOGY is increasing in RF design applications owing to the promise of integrating electronic systems on a single silicon chip. While complete broad band characterization and accurate modeling of the MOSFET noise are critical requirements for circuit designs, the noise behavior and physics in short channel MOSFETs is not well understood. This dissertation explores the physical origin and contributing mechanisms of noise in MOSFETs, as well as a design methodology to minimize the impact of noise on fully integrated LNAs. Investigating the physical noise sources in the MOSFET imposes significant computational requirements, due to the multi-dimensional nature of the device. In addition, higher order transport models need to be considered due to aggressive channel-length scaling. This dissertation presents a quasi two-dimensional noise simulation technique which provides an accurate and fast solution for MOSFET noise analysis by combining a 1-D active transmission line model with rigorous 2-D device simulation. The physical origin of the excess noise in short channel MOSFETs has been identified. Source-side contributions dominate drain current noise; non-local transport behavior causes higher local ac resistance near the source junction and in turn generates extra noise contributions which are amplified by the channel transconductance. This phenomenon is directly reflected in excess values and a strong gate length dependence of γ and δ in scaled submicron MOSFETs. Higher order transport models are essential to capture this effect in v noise simulation. Contrary to the common assumption that drain current exhibits only 1/f and white channel thermal noise contributions, this study demonstrates that the substrate generates thermal fluctuations that produce additive channel noise, amplified by the substrate transconductance. This component produces another plateau and frequency dependence in the noise spectrum of the drain current. Moreover, the effect tends to exaggerate the drain noise factor at low frequencies. The high frequency noise modeling for MOSFET devices generally requires at least three parameters. This study demonstrates that while other two-parameter approaches, such as developed by Pospieszalski and those used in BSIM4 model, lead to errors, the results do not cause noticeable discrepancies for most practical circuit topologies. The modeling approach used in BSIM4 has been independently validated and is shown to be sufficient in capturing the physical origin of the excess noise. Explicit guidelines for LNA design have been presented based directly on measured noise parameters and two-port noise theory; the approach requires neither sophisticated noise modeling nor circuit simulation. An 800MHz LNA test chip has been designed based on the proposed methodology. With 3.75mA of bias current, the LNA achieves about 0.9dB of noise figure, which adds just 0.3dB to the NFmin of the intrinsic MOSFET device. It is competitive with that of GaAs and bipolar LNAs and also quite close to the values predicted using the analysis presented in this work.

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High frequency noise in CMOS low noise amplifiers

The Impedance Field Method (IFM) for physics-based noise modeling of electron devices is applied, for the first time, to evaluate the RF noise performance of submicron MOSFETs Starting with an accurate representation of the structure and doping of devices from a 025 /spl mu/m CMOS technology, we present the behavior of the drain and gate power and correlation noise spectra, as a function of frequency and gate length The simulations are shown to be in agreement with measured noise parameters

H.H. Vuong

Papers

Physics-based RF noise modeling of submicron MOSFETs