A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

Protocol for communication with dynamic memory

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

The present invention is directed to a method of operating a memory device wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to a first external clock signal and a second external clock signal. In one preferred embodiment, the method may further include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory device. In this preferred embodiment, the first amount of data corresponding to the first block size information is output after the number of clock cycles of the first and second external clock transpire. The number of clock cycles may be a whole number or a fraction.

Method of operating a synchronous memory having a variable data output length

A dual port digital memory system, which includes integral memory sequencing circuitry (22), is controlled by a bit-serial address and control signal (SAD). The address and control signal, which includes a data read address, a data write address and a control value, is serially loaded into a shift register (10). The address sequencing circuitry loads the read and write address values into integral read (24) and write (26) address registers and, based on the control value, initiates respective read and/or write operations.

Dual port video memory system having a bit-serial address input port

A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Parallel access virtual channel memory system

High-speed operation, a 33-MHz serial cycle, and a 10-ns serial data access time have been realized by internal serial/parallel conversion circuits, a newly designed I/O controller circuit, new dynamic register circuits, a divided sensing method, and an optimized layout design. The chip is fabricated with a 1.2-/spl mu/m double-level polysilicon and double-level aluminium n-channel MOS process technology. An optimized interlevel insulator realizes equivalent first- and second-level aluminium pitches for a compact chip design. The chip size is 5.88/spl times/11.2 mm/SUP 2/. This memory has high-speed input and output capability as well as random accessibility. These features are suitable for TV and VCR frame-memory-system applications.

A 1-Mbit DRAM with 33-MHz serial I/O ports

THIS PAPER WILL DESCRIBE a 1Mb image memory, 256k x 4 DRAM with 30ns bit rate serial 1/0 ports with special features for TV or VCR image display applications. In this development, 4b wide data are shifted into 4 sets of 8 b shift registers, loaded from the DRAM to other 4 sets of 8b shift registers and shifted out through serial ports. These operations are performed under 33MHz clock without any idle time. One field of a color TV signal has 256k x 8b, so that only two chips of this memory are enough to store it. A block diagram of the memory is shown in Figure 1. The DRAM block is constructed with 512 rows and 2,048 columns. 2,048 columns are divided into 4 groups, and each group has 64 x 8b columns. Serial data handling block is constructed with four sets of 8 I/O selectors, 8b serialin and serial-out registers. Figure 2 shows the timing diagram of this memory. In the write cycle, input data are shifted into an 8 b serial-in register by synchronizing the rising edge ofSIC clock through data input pins, D l 1 to D14. At the falling edge of WS clock, 32b data in four 8b serial-in re&ers are transfered to 32b data registers. And at the falling edge of WE clock, 32b data go through I/O selectors and to 32b memory cells which have been selected and activated by IS &dress pins (A0 A14), a chip select pin (CS), and a chip enable pin (CE). In the read mode, readout data from the selected address are sensed, go through I/O selectors and are loaded on four 8b serial out registers at the falling edge of RS clock. Data from the serial out registers are shifted out serially at every rising edge of SOC clock through data

http://ieeexplore.ieee.org/iel6/8301/25933/01157012.pdf

H. Kawai

Papers

A 1-Mbit DRAM with 33-MHz serial I/O ports

A 1Mb DRAM with 33MHz serial I/O ports