In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

In this paper, we present a new electromigration reliability diagnosis tool (iTEM) for CMOS VLSI circuits. Unlike previous electromigration reliability tools, iTEM can estimate the interconnect temperature rise due to joule heating and heat conduction from the substrate using a newly developed lumped thermal model. By including the temperature effect, iTEM provides much more accurate electromigration reliability diagnosis. Moreover, it is computationally efficient, and can analyze circuit layouts containing tens of thousands of transistors on a desktop workstation.

iTEM: a temperature-dependent electromigration reliability diagnosis tool

One of the crucial steps in the design of an integrated circuit is the minimization of heating and temperature non-uniformity. Current temperature calculation methods, such as finite element analysis and resistor networks have considerable computation times, making them incompatible for use in routing and placement optimization algorithms. In an effort to reduce the computation time, we have developed a new method, deemed power blurring, for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. For steady state analysis, power blurring was able to predict hot spot temperatures within 1°C with computation times 3 orders of magnitude faster than FEA. For transient analysis the computation times where enhanced by a factor of 1000 for a single pulse and around 100 for multiple frequency application, while predicting hot spot temperature within about 1°C. The main strength of the power blurring technique is that it exploits the dominant heat spreading in the silicon substrate and it uses superposition principle. With one or two finite element simulations, the temperature point spread function for a sophisticated package can be calculated. Additional simulations could be used to improve the accuracy of the point spread function in different locations on the chip. In this calculation, we considered the dominant heat transfer path through the back of the IC chip and the heat sink. Heat transfer from the top of the chip through metallization layers and the board is usually a small fraction of the total heat dissipation and it is neglected in this analysis.

http://documents.irevues.inist.fr/bitstream/handle/2042/6586/UTP133.pdf?sequence=1

Ultrafast temperature profile calculation in ic chips

Optical interface multichip module (MCMs) and optical interface ball grid array (BGA) packages promise to overcome the bottleneck of electrical interconnection. This will lead to telecommunications systems that have throughput exceeding several terabits per second and computer systems having speeds of several gigahertz. A national project has resulted in the development of over-100-Gb/s optoelectronic MCM (OE-MCM) packaging technologies, which will play a key role in the construction of terabits per second hardware systems. The packaging technologies feature a 10-cm square OE integrated substrate containing low-loss optical waveguides and filled vias formed by laser drilling and electroplating for improved heat dissipation, which allow higher device densities. Reliable and stable flip-chip device packaging has also been developed. This packaging features accurate photonic device bonding by microsolder bumps, low loss optical coupling using reflection mirrors, and an optical underfill technique to reduce optical reflection noise. Optical interface BGA packages using microlenses for optical input or output terminals allow high-density board packaging because of the fiberless optical interface and wide misalignment tolerances of /spl plusmn/100 /spl mu/m, which is compatible with current electronic assembly techniques. It is expected that the BGA packages will be widely developed for high-density low-cost packaging on boards.

Optoelectronic multichip module packaging technologies and optical input/output interface chip-level packages for the next generation of hardware systems

Thermal management is critical to reliable optoelectronic modules based on vertical-cavity surface-emitting lasers (VCSELs). One critical thermal path to be managed is from a VCSEL to a case (heat sink), which is affected by packaging technologies and materials The measured VCSEL-to-case resistance of a laser with 8-/spl mu/m aperture was 1650/spl deg/C/W, and that of a 20-/spl mu/m device was 1070/spl deg/C/W. These thermal resistances are much larger than those for the edge-emitting lasers; advanced device and packaging technologies are being developed to reduce these resistances. To study the packaging effects, a three-dimensional (3-D) numerical model has been developed and calibrated by the measured data. The calibrated model was used to understand the difference in thermal behavior: 1) between a wire-bonded and a flip-chip VCSEL module, 2) between a single-VCSEL and an 8/spl times/8 VCSEL module, and 3) between a bottom-cooled and a top-cooled module.

Thermal management of VCSEL-based optoelectronic modules

A heat-transfer study is conducted for the steady-state internal thermal resistance of a multichip packaging technology for VLSI-based systems. This technology, which is known as advanced VLSI packaging (AVP), has chips flip-chip soldered and interconnected on a silicon substrate. AVP's thermal management approach is to dissipate chip power through the silicon substrate to a heat sink or other packaging levels. The authors found a need to control the chip-to-substrate interface; therefore, they use a three-dimensional heat conduction analysis to characterize this interface. They simulate thermal performance of typical AVP assemblies affected by thermal vias, solder bump heights, high-power I O drivers, and chip sizes. The authors also analyze and measure the internal resistances of an experimental package consisting of three WE32100 chips. These resistances are predicted as 3.7, 4.7, and 5.0 degrees C/W, respectively; they are confirmed by the experimental data. The authors demonstrate the low thermal resistance achieved: 3.0 degrees C/W for a 1-cm square chip and 10 degrees C/W for a 0.25-cm square chip. They also provide their insight into the roles of different conduction paths involved. >

H.T. Ghaffari

Papers

Internal thermal resistance of a multi-chip packaging design for VLSI-based systems