Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

Equalization and decision-directed loops with trellis demodulation in high definition TV

Low power signal processing systems are required for distributed network microsensor technology. Network microsensors now provide a new monitoring and control capability for civil and military applications in transportation, manufacturing, biomedical technology, environmental management, and safety and security systems. Signal processing methods for event detection have been developed with low power, parallel architectures that optimize performance for unique sensor system requirements. Implementation of parallel datapaths with shared arithmetic elements enables high throughput at low clock rate. This method has been used to implement a microsensor spectrum analyzer for a 200 sample/s measurement system. This 0.8 /spl mu/ CMOS device operates with a 1 /spl mu/A drain current at a 3 V supply bias.

Low power signal processing architectures for network microsensors

This paper discusses typical architectures and challenges in designing integrated circuits for data transmission over twisted-pair wire channels. To highlight the various architectural approaches, two main applications are discussed-high-bit-rate digital subscriber loop (HDSL) and fast-Ethernet. Although these two applications have orders of magnitude difference in their bit rates, they share many common building blocks including line-drivers, 24 wire hybrids, echo cancellation, digital equalization, and clock recovery. Typical integrated circuit approaches for realizing each of these blocks are presented as well as possible tradeoffs. Finally, future challenges facing integrated circuit designers are presented.

Integrated circuits for data transmission over twisted-pair channels

A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

Dual mode QAM/VSB receiver

Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fc=fS/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.

Timing recovery using the pilot signal in high definition TV

A 60-MHz 64-tap adaptive finite-impulse-response (FIR) filter chip was fabricated in 1.2- mu m CMOS. It can implement either an echo canceler or a decision feedback equalizer for 2B1Q high bit rate digital subscriber line (HDSL) transceivers. The 4.3*4.3 mm/sup 2/, 30000 transistor chip is a completely self-contained adaptive filter which incorporates the least mean square (LMS) algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths, which are often required in high bit rate transceivers. At a 60-MHz clock rate, the echo canceler/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud. >

A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers

A 60-MHz 64-tap adaptive FIR filter chip has been fabricated in 1.2- mu m CMOS which can implement either an echo canceller or decision-feedback equalizer for 2B1Q high bit-rate digital subscriber line (HDSL) transceivers. The 4.3-mm*4.3-mm, 30000-transistor chip is a complete self-contained adaptive filter which incorporates the LMS algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths which are often required in high-bit-rate transceivers. At a 60-MHz clock rate the echo canceller/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud. >

H.T. Nicholas

Papers

A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers

A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceivers