Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

Equalization and decision-directed loops with trellis demodulation in high definition TV

The authors describe automatic architecture and floorplan generation techniques for integrated circuit fixed-coefficient FIR (finite impulse response) filters that can achieve high sample rates with compact layouts. These techniques have been implemented in a filter design system called FIRGEN that can automate the entire design from filter specifications to final chip layout. It can be retargeted to new cell libraries and place and route tools. Result on four chips designed with FIRGEN are presented. These achieve sample rates ranging from 25 MHz to 112 MHz. >

FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits

A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

Dual mode QAM/VSB receiver

Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fc=fS/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.

Timing recovery using the pilot signal in high definition TV

LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout, and, with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high-sample-rate applications. A number of algorithm-specific ICs designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip are described. >

https://ir.nctu.edu.tw:443/bitstream/11536/3821/1/A1991FE74800004.pdf

An integrated CAD system for algorithm-specific IC design

A 60-MHz 64-tap adaptive FIR filter chip has been fabricated in 1.2- mu m CMOS which can implement either an echo canceller or decision-feedback equalizer for 2B1Q high bit-rate digital subscriber line (HDSL) transceivers. The 4.3-mm*4.3-mm, 30000-transistor chip is a complete self-contained adaptive filter which incorporates the LMS algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths which are often required in high-bit-rate transceivers. At a 60-MHz clock rate the echo canceller/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud. >

A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceivers

A novel functional compiler, FIRGEN, for automatic generation of finite-impulse response (FIR) filters using custom and gate-array technologies is described. It consists of CAD tools to automate the entire design from filter specifications to final chip layout. The architecture and floorplan description generation by FIRGEN can be used to drive custom macrocell or gate-array place and route tools to generate the final layout. A unique feature of the compiler is that it uses architecture and floorplanning techniques that are targeted at FIR filters with sample rates in the region 10-100 MHz for video and digital communication applications. Results of three chips designed with FIRGEN are presented. >

http://ieeexplore.ieee.org/iel2/140/3519/00124737.pdf

L.K. Tan

Papers

A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceivers

FIRGEN: a CAD system for automatic layout generation of high-performance FIR filter