Recent trends in digital communications are opening commercial applications to code division multiple access (CDMA). A novel access technique based on bandlimited quasi-synchronous CDMA (BLQS-CDMA) is described, showing all the advantages of synchronizing conventional direct sequence CDMA to drastically reduce the effect of self-noise. Bandlimitation is achieved with no detection loss by means of Nyquist chip shaping, leading to a simple all-digital demodulator structure. Detection losses due to imperfect carrier frequency and chip timing synchronization are analytically derived and numerical results are checked by computer simulations. Impairments due to satellite transponder distortions are evaluated. The full digital modem structure is presented, together with possible applications to mobile and very small aperture terminal (VSAT) satellite communications. >

Bandlimited quasi-synchronous CDMA: a novel satellite access technique for mobile and personal communication systems

Recent dramatic improvements in integrated circuit fabrication technology have led to Field-Programmable Gate Arrays (FPGAs) capable of implementing entire digital systems, as opposed to the smaller logic circuits that have traditionally been targeted to FPGAs. Unlike the smaller circuits, these large systems often contain memory. Architectural support for the efficient implementation of memory in next-generation FPGAs is therefore crucial.
This dissertation examines the architecture of FPGAs with memory, as well as algorithms that map circuits into these devices. Three aspects are considered: the analysis of circuits that contain memory, as well as the automated random generation of such circuits, the architecture and algorithms for stand-alone configurable memory devices, and architectures and algorithms for the embedding of memory arrays in an FPGA.
We first present statistics gathered from 171 circuits with memory. These statistics include the number of memories in each circuit and the width and depth of these memories. We identify common interconnect patterns between memory and logic. These statistics are then used to develop a circuit generator that stochastically generates realistic circuits with memory that can be used as benchmark circuits in architectural studies.
Next, we consider the architecture of a stand-alone configurable memory that is flexible enough to implement memory configurations with different numbers of memories, memory widths and depths. Instrumental in this work is the algorithms that map memory configurations to the device. These algorithms are used in an experimental framework to investigate the effect of various architectural parameters on the flexibility, chip area, and access time of the configurable memory.
Finally, the architecture of an FPGA containing both embedded memory arrays and logic elements is considered, along with new automatic placement and routing algorithms that map circuits to the FPGA. We show that only 4 switches per memory block pin are required in the interconnection between the memory arrays and logic elements, and even lower in FPGAs with four or fewer memory arrays. In addition, we show that by providing direct connections between memory arrays, the FPGA density can be improved slightly, and the average memory access time can be improved by as much as 25%.

Architectures and algorithms for field-programmable gate arrays with embedded memory

A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.

Integrating receiver with precharge circuitry

A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1- mu m CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz. >

An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS

An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator

Method and apparatus for receiving high-speed signals with low latency

An all-digital architecture is presented for implementing the front-end signal-processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25- mu m process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR (finite-impulse response) square-root Nyquist matched filters, and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256*256 points. Thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using formats such as M-ary PSK and QAM. >

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A VLSI architecture for a high-speed all-digital quadrature modulator and demodulator for digital radio applications

A 60-MHz 64-tap adaptive finite-impulse-response (FIR) filter chip was fabricated in 1.2- mu m CMOS. It can implement either an echo canceler or a decision feedback equalizer for 2B1Q high bit rate digital subscriber line (HDSL) transceivers. The 4.3*4.3 mm/sup 2/, 30000 transistor chip is a completely self-contained adaptive filter which incorporates the least mean square (LMS) algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths, which are often required in high bit rate transceivers. At a 60-MHz clock rate, the echo canceler/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud. >

A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers

A monolithic custom digital signal processor which satisfies both the US and the European standards for HDSL (high-bit-rate digital subscriber line) transmission is presented. The architecture of an HDSL transceiver is shown. At the receiver, the ADC (analog-to-digital converter) samples the signal once per symbol period. The transmit energy is removed using an echo canceller. The resulting receive energy is then prefiltered and sent to the feedforward equalizer (FFE). The FFE provides gain and removes any precursor intersymbol interference (ISI). The decision-feedback equalizer then removes the postcursor ISI. The resulting data are sliced into a symbol decision and error value. >

A 1 Mb/s digital subscriber line transceiver signal processor

A 60-MHz 64-tap adaptive FIR filter chip has been fabricated in 1.2- mu m CMOS which can implement either an echo canceller or decision-feedback equalizer for 2B1Q high bit-rate digital subscriber line (HDSL) transceivers. The 4.3-mm*4.3-mm, 30000-transistor chip is a complete self-contained adaptive filter which incorporates the LMS algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths which are often required in high-bit-rate transceivers. At a 60-MHz clock rate the echo canceller/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud. >

B.C. Wong

Papers

A VLSI architecture for a high-speed all-digital quadrature modulator and demodulator for digital radio applications

A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers

A 1 Mb/s digital subscriber line transceiver signal processor

A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceivers