Intuition, device evolution, and even efficient computation require simple MOSFET (metal-oxide-semiconductor field-effect transistor) models. Among these simple models are charge-sheet models which compress the inversion layer into a conducting plane of zero thickness. It is the purpose of this paper to test one such charge sheet model to see whether this approximation is too severe. This particular model includes diffusion which is expected to be important in the subthreshold and saturation regions. As a test the charge sheet model is applied to long-channel devices. Long-channel MOSFET behavior has been thoroughly studied, and is very well explained by the Pao-Sah double-integral formula for the current. Hence, a clear-cut test is a comparison of the charge sheet model with the Pao-Sah model. We find the charge sheet model has two advantages over the Pao-Sah model. (1) It leads to a very simple algebraic formula for the current of long-channel devices. The same formula applies in all regimes from subthreshold to saturation. Neither splicing nor parameter changes are needed. No discontinuities occur in either the current or the small-signal parameters, or in the derivatives of the small-signal parameters. (2) It is simpler to extend the charge sheet model to two or three dimensions than the Pao-Sah model. This simplification is a result of dropping the details of the inversion layer charge distribution. An important aspect of the gradual channel approximation is brought out by the analysis. Suppose the boundary condition relating the quasi-fermi level at the drain, φfL, to that at the source, φfo, namely φ ƒL =φ ƒ0 +V D where VD is the drain voltage, is applied in all bias regimes. Then it is shown that this means the potential at the drain end of the channel, φsL is not related to the potential at the source end of the channel, φso, by φ sL =φ s0 +V D Instead, φsL is computed, not imposed as a boundary condition. It is suggested that this failure of the potential to satisfy the boundary condition at the drain is justifiable. That is, φsL should be reinterpreted as the potential at the point in the channel where the gradual channel approximation fails. Hence, (2) may be relaxed. However, the “channel length” in the gradual-channel approximation now becomes a fitting parameter and is not the metallurgical source-to-drain separation. In addition several aspects of the long-channel MOSFET are brought out: (1) Pinch-off is achieved only asymptotically as the drain voltage tends to infinity. This is in marked contrast to the often-stated, textbook view that pinch-off is achieved for some finite drain voltage, the saturation voltage. (2) The channel or drain conductance approaches zero only asymptotically. (3) The transconductance saturates only asymptotically. Figures comparing the simple charge-sheet model formulas with the usual textbook formulas are included for direct-current vs drain voltage, channel conductance vs drain voltage, and transconductance vs drain voltage. The charge-sheet model agrees with the original Pao-Sah double-integral formula for the current at all gate and drain voltages, and possesses the correct subthreshold behavior. The textbook formulas do not.

A charge-sheet model of the MOSFET

The operation of the ferroelectric nonvolatile memory field effect transistor is theoretically examined extensively for the first time. The ferroelectric transistor device properties are derived by combining the silicon charge‐sheet model of metal‐oxide‐semiconductor field‐effect transistor device operation with Maxwell’s first equation which describes the properties of the ferroelectric film. The model we present describes ferroelectric transistor I‐V and C‐V behavior when time‐dependent voltages are applied which result in hysteresis due to ferroelectric switching. The theoretical results provide unique insight into the effects of geometrical and material parameters on the electrical properties of the transistor. These parameters include the ferroelectric spontaneous and remanent polarization, the coercive field, and dielectric layer thicknesses. We have found that the conventional concept of threshold voltage is no longer useful, and that increasing the spontaneous polarization has only a minor impact ...

Physics of the ferroelectric nonvolatile memory field effect transistor

A model is developed for an IGFET operating in saturation and accounting for the two-dimensional potential distribution in the section of the surface space-charge region adjacent to the drain. This section is treated as a volume obeying Gauss's law, thereby enabling the charge contained in it to be related to the integral of the electric displacement density normal to its surface without the need to consider the detailed distribution of charge inside. The resulting model shows, explicitly, the dependence of device output characteristics on applied potentials, geometric and processing parameters. It is also shown that by making adequate approximations, simple yet accurate forms of the model are obtained. The accuracy of the model is demonstrated by comparisons between calculated and measured device output characteristics.

A simple two-dimensional model for IGFET operation in the saturation region

Techniques are presented for calculating the drain current of small-geometry MOSFET's in the linear, subthreshold, and punch-through regions of device operation. The current calculation depends only on the electrostatic solution of the two-dimensional Poisson equation in the device. The accuracy of the techniques is established by comparisons with full two-dimensional simulations based on the simultaneous solution of the Poisson and minority-carrier current-continuity equations. The results of simulation also agree well with measurements on MOSFET's having submicrometer effective channel lengths. The application of the simulations to nonplanar technologies is illustrated by the analysis of a taper-isolated dynamic-gain RAM cell. A description is given of simple numerical techniques for solving Poisson's equation in the presence of nonplanar boundaries. The solution method demonstrates good convergence characteristics and minimizes computer storage requirements. Consequently, the simulation capabilities have been successfully implemented on a desktop calculator (Hewlett-Packard 9845) and on minicomputers (Hewlett-Packard 2100 and 1000-F).

Nonplanar VLSI device analysis using the solution of Poisson's equation

A new n-channel silicon MOS transistor is described that can be fabricated with channel lengths of less than 1 µ by using a double-diffusion process similar to that used in bipolar transistor fabrication. The dimensional tolerances are not tighter than those used in the processing of conventional MOS transistors. This device (called D-MOST) shows gain in the GHz range and a noise figure comparable to that of microwave transistors. The f max is 10 GHz and the noise figure is 4.0 dB at 1 GHz. A brief theory of the D-MOST is followed by the design considerations for a discrete microwave device. Results from s-parameter measurements in the range of 0.1-2.5 GHz are presented along with graphs showing the gains and the stability factor. A simple equivalent circuit is derived from the measurements. Applications of the D-MOST are described.

D-MOS transistor for microwave applications

A model for inversion-layer m.o.s.t.s is outlined which avoids the usual gradual-channel approximation by the use of 2-dimensional solutions to the Shockley-Poisson and Laplace equations governing the field distribution. Computed I/V and C/V characteristics and potential-distribution; diagrams are shown for a particular device geometry.

H.W. Loeb

Papers

Application of 2-dimensional solutions of the Shockley-Poisson equation to inversion-layer m.o.s.t. devices