The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits.

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A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.

A versatile CMOS linear transconductor/square-law function

Real time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been available for some time, the CMOS multiplier implementation is still a challenging subject especially for low-voltage and low-power circuit design. Despite the large number of papers proposing new CMOS multiplier structures, they can be roughly grouped into a few categories. This tutorial provides a complete survey of CMOS multipliers, presents a unified generation of multiplier architectures, and proposes the most recommended MOS multiplier structure. This tutorial could serve as a starting reference point (and metric) for comparison of new CMOS multiplier circuit configurations. An illustrative CMOS chip prototype verifying theoretical results is presented.

CMOS transconductance multipliers: a tutorial

An MOS four-quadrant analog multiplier is described. It is based on the square-law dependence of the MOS-transistor drain current on the gate-to-source voltage in the saturation region. One input is applied to the gate directly while the other input is applied to the source through a source-follower buffer stage. The circuit is realized with only 12 MOS transistors and two resistors. The circuit has been fabricated using a metal-gate NMOS process which has separate p-wells to eliminate the substrate bias effect. The multiplier achieves less than 0.45% nonlinearity when the input voltage range is 40% of the supply voltages, and it achieves a -3-dB bandwidth of 30 MHz. The total harmonic distortion is less than 0.6%. The power consumption and chip size are 8 mW and 1.2 mm/sup 2/, respectively. The second-order effects for this type of multiplier are considered in detail. >

An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers

A circuit configuration for a four-quadrant analog multiplier in MOS integrated circuit technology is described. It is based on the quarter-square algebraic identity and uses differential summer and differential squaring stages. The multiplier achieves a linearity of 0.44%, a -3-dB bandwidth of 5 MHz, a dynamic range of 87 dB, and a total harmonic distortion of 0.59%. The circuit was fabricated in a 5-/spl mu/m double-polysilicon p-well CMOS process. Typical power consumption is 10 mW. Chip size is 500 mil/SUP 2/.

A MOS four-quadrant analog multiplier using the quarter-square technique

A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.

H. Wallinga

Papers

A CMOS Four-Quadrant Analog Multiplier