This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2 m ) This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial multiplier, and two programmable processors Through reconfiguration, the squarer and the multiplier architectures can be optimized for any field order or field polynomial The multiplier performance can also be scaled according to system's needs Our results show that implementations of this architecture executing the projective coordinates version of the Montgomery scalar multiplication algorithm can compute elliptic curve scalar multiplications with arbitrary points in 021 msec in the field GF(2 167 ) A result that is at least 19 times faster than documented hardware implementations and at least 37 times faster than documented software implementations

A high-performance reconfigurable elliptic curve processor for GF(2m)

Training deep learning models is compute-intensive and there is an industry-wide trend towards hardware specialization to improve performance. To systematically benchmark deep learning platforms, we introduce ParaDnn, a parameterized benchmark suite for deep learning that generates end-to-end models for fully connected (FC), convolutional (CNN), and recurrent (RNN) neural networks. Along with six real-world models, we benchmark Google's Cloud TPU v2/v3, NVIDIA's V100 GPU, and an Intel Skylake CPU platform. We take a deep dive into TPU architecture, reveal its bottlenecks, and highlight valuable lessons learned for future specialized system design. We also provide a thorough comparison of the platforms and find that each has unique strengths for some types of models. Finally, we quantify the rapid performance improvements that specialized software stacks provide for the TPU and GPU platforms.

Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

The radial basis function (RBF) network has its foundation in the conventional approximation theory. It has the capability of universal approximation. The RBF network is a popular alternative to the well-known multilayer perceptron (MLP), since it has a simpler structure and a much faster training process. In this paper, we give a comprehensive survey on the RBF network and its learning. Many aspects associated with the RBF network, such as network structure, universal approimation capability, radial basis functions, RBF network learning, structure optimization, normalized RBF networks, application to dynamic system modeling, and nonlinear complex-valued signal processing, are described. We also compare the features and capability of the two models.

/pdf/using-radial-basis-function-networks-for-function-1bb48uzio8.pdf

Using Radial Basis Function Networks for Function Approximation and Classification

A power efficient multirate multistage Comb decimation filter for mono-bit and multi-bit /spl Sigma//spl utri/ A/D converters is presented Polyphase decomposition in all stages, with high decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb filter Several implementations indicate that proper choice of the first stage decimation factor can considerably improve power consumption, area and maximum sampling frequency In multibit /spl Sigma//spl utri/ A/Ds, this optimum first stage decimation factor is a function of the input wordlength

Efficient polyphase decomposition of comb decimation filters in /spl Sigma//spl utri/ analog-to-digital converters

This paper presents a new sharpened comb decimator structure consisting of a cascade of a comb-filter based decimator and a sharpened comb decimator. The proposed realization scheme allows the sharpened section to operate at a lower rate that depends on the decimation factor of the first section. Using a polyphase decomposition, the subfilters of the first section can also be operated at this lower rate.

A new two-stage sharpened comb decimator

This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.

https://downloads.hindawi.com/journals/ijrc/2009/259837.pdf

FPGA interconnect topologies exploration

Field Programmable Gate Arrays (FPGAs) were first introduced almost two and a half decades ago. Since then they have seen a rapid growth and have become a popular implementation media for digital circuits. The advancement in process technology has greatly enhanced the logic capacity of FPGAs and has in turn made them a viable implementation alternative for larger and complex designs. Further, programmable nature of their logic and routing resources has a dramatic effect on the quality of final device’s area, speed, and power consumption.

FPGA Architectures: An Overview

This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures.

Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization

A power efficient multi-rate multi-stage Comb decimation filter for mono-bit and multi-bit /spl Sigma//spl Delta/ A/D converters is presented. Polyphase decomposition in all stages, with high decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb filter. Several implementations indicate that proper choice of the first stage decimation factor can considerably improve power consumption, area and maximum sampling frequency. In multibit /spl Sigma//spl Delta/ A/Ds, this optimum first stage decimation factor is function of the input wordlength.

/pdf/efficient-polyphase-decomposition-of-comb-decimation-filters-pak94jpdqa.pdf

Habib Mehrez

Papers

Efficient polyphase decomposition of comb decimation filters in /spl Sigma//spl utri/ analog-to-digital converters

FPGA interconnect topologies exploration

FPGA Architectures: An Overview

Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization

Efficient polyphase decomposition of Comb decimation filters in /spl Sigma//spl Delta/ analog-to-digital converters