With the data rate of high-speed links increasing, the impact of nonlinear factors becomes more and more prominent that bring great signal integrity challenges to the analysis and design of high-speed links. However, there are two gaps in the study of the nonlinear behaviors of the high-speed links. One is that there is no simulation platform that can flexibly deal with different kinds of nonlinear behaviors. The other is that there is no metric that can quantify the level of the nonlinearity of the links. Aiming at these two problems, this article first models a nonlinear high-speed link based on Simulink, which can flexibly adjust the nonlinear behaviors, and then analyze the impact of nonlinear behaviors on the performance of high-speed links. Lastly, a metric is presented based on the principal component analysis to quantify the level of the nonlinearity of the high-speed links. Simulation results show that the metric can effectively capture the nonlinear severity of the links.

Simulink-Based Modeling and PCA-Based Nonlinearity Evaluation for High-Speed Links

As the degree of nonlinearity in high-speed links becomes more and more serious, traditional decision feedback equalization (DFE) which is based on linear time-invariant assumption can no longer eliminate the inter-symbol interference effectively. In this paper, the shortcomings of traditional DFE structure for nonlinear high-speed links are first analyzed. Then, the multi-bit response (MBR) method is proposed to accurately construct the bit stream responses of the nonlinear high-speed links. Lastly, a novel DFE structure based on the MBR method is presented to improve the signal quality of the nonlinear high-speed links. The accuracy of the proposed method is verified by the simulation based on a nonlinear high-speed link model. Compared with traditional DFE, the proposed DFE structure can significantly improve the signal quality of the nonlinear high-speed links. As the degree of nonlinearity increases, the advantage of the proposed DFE becomes more prominent.

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A Novel Decision Feedback Equalization Structure for Nonlinear High-Speed Links

As data rates of high-speed links increase, the impact of nonlinearity is becoming more and more prominent. To capture the effect of nonlinear behaviors on the system response, the multiple edge response (MER) method was proposed for nonlinear systems. High order MER can capture sufficient nonlinearity and achieve accurate results. However, it is quite time-consuming to obtain a large amount of edge responses for the higher order MER. Therefore, it is necessary to study the minimum required order of MER to estimate the system performance. In this work, a simple and efficient method based on multiple pulse responses is proposed to estimate the minimum required order of MER. The accuracy of the proposed method is validated by simulation for a nonlinear high-speed link.

Order Determination of the Multiple Edge Response Method for Nonlinear Links

The rapid demand for higher density and higher data rate Serdes signals in a single high-speed integrated circuit (IC) package is continuously expanding for emerging data-center, networking and storage applications. Hence, this paper discusses cost-effective substrate design solution for high-density 56Gbps PAM4 channels in a single package by enabling back-side trace design strategy. This is critical for low die-package size ratio packages whereby the die edge is close to package edge owing to package form factor constraint. The package transceivers signal layer-to-layer impedance change, and via-to-via coupling are carefully studied using 3D full-wave electromagnetic (EM) tool solver for optimal performance to meet package electrical specifications. By implementing the proposed back-side trace design strategy, it is estimated to potentially save up to 25% substrate cost comparing to the baseline design owing to package layer count reduction and package size increase avoidance.

High-Density 56Gbps PAM4 Package Design Enablement with Cost and Performance Optimization

The rapid demand for higher density and higher data rate Serdes signals in a single high-speed integrated circuit (IC) package is continuously expanding for emerging data-center, networking and storage applications. Hence, this paper discusses cost-effective substrate design solution for high-density 56Gbps PAM4 channels in a single package by enabling back-side trace design strategy. This is critical for low die-package size ratio packages whereby the die edge is close to package edge owing to package form factor constraint. The package transceivers signal layer-to-layer impedance change, and via-to-via coupling are carefully studied using 3D full-wave electromagnetic (EM) tool solver for optimal performance to meet package electrical specifications. By implementing the proposed back-side trace design strategy, it is estimated to potentially save up to 25% substrate cost comparing to the baseline design owing to package layer count reduction and package size increase avoidance. 

With the data rate of high-speed links increasing, the impact of nonlinear factors becomes more and more prominent, which bring great signal integrity challenges to the analysis and design of high-speed links. However, there are two gaps in the study of the nonlinear behaviors of the high-speed links. One is that there is no simulation platform which can flexibly deal with different kinds of nonlinear behaviors. The other is that there is no metric which can quantify the level of the nonlinearity of the links. Aiming at these two problems, this paper first models a nonlinear high-speed link based on Simulink, which can flexibly adjust the nonlinear behaviors and analyze the impact of nonlinear behaviors on the performance of the high–speed links. Then a metric is presented base on the principal component analysis (PCA) to quantify the level of the nonlinearity of the high-speed links. Simulation results show that the metric can effectively capture the nonlinear severity of the links.

Modeling and Analysis of Nonlinear High-Speed Links

This paper will walk-through the process and challenges of design and integration of 56G PAM4 PHY into a low cost SoC package and platform targeting 5G base stations market. In order to deliver best in class design and meet strict electrical compliance from both the SerDes designer and the IEEE802.3 standards, an amalgamation of signal integrity optimization techniques are addressed in this paper.

Hank Wu

Papers

Modeling and Analysis of Nonlinear High-Speed Links

High Performance Low Cost Package and Platform Design for 56G PAM4 SerDes