Low Cost Cryptography.- Quark: A Lightweight Hash.- PRINTcipher: A Block Cipher for IC-Printing.- Sponge-Based Pseudo-Random Number Generators.- Efficient Implementations I.- A High Speed Coprocessor for Elliptic Curve Scalar Multiplications over .- Co-Z Addition Formulae and Binary Ladders on Elliptic Curves.- Efficient Techniques for High-Speed Elliptic Curve Cryptography.- Side-Channel Attacks and Countermeasures I.- Analysis and Improvement of the Random Delay Countermeasure of CHES 2009.- New Results on Instruction Cache Attacks.- Correlation-Enhanced Power Analysis Collision Attack.- Side-Channel Analysis of Six SHA-3 Candidates.- Tamper Resistance and Hardware Trojans.- Flash Memory 'Bumping' Attacks.- Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection.- When Failure Analysis Meets Side-Channel Attacks.- Efficient Implementations II.- Fast Exhaustive Search for Polynomial Systems in .- 256 Bit Standardized Crypto for 650 GE - GOST Revisited.- Mixed Bases for Efficient Inversion in and Conversion Matrices of SubBytes of AES.- SHA-3.- Developing a Hardware Evaluation Method for SHA-3 Candidates.- Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.- Performance Analysis of the SHA-3 Candidates on Exotic Multi-core Architectures.- XBX: eXternal Benchmarking eXtension for the SUPERCOP Crypto Benchmarking Framework.- Fault Attacks and Countermeasures.- Public Key Perturbation of Randomized RSA Implementations.- Fault Sensitivity Analysis.- PUFs and RNGs.- An Alternative to Error Correction for SRAM-Like PUFs.- New High Entropy Element for FPGA Based True Random Number Generators.- The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes.- New Designs.- Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs.- ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware.- Side-Channel Attacks and Countermeasures II.- Provably Secure Higher-Order Masking of AES.- Algebraic Side-Channel Analysis in the Presence of Errors.- Coordinate Blinding over Large Prime Fields.

Cryptographic hardware and embedded systems : CHES 2010 : 12th international workshop, Santa Barbara, USA, August 17-20, 2010 : proceedings

In this paper we will present the concept of a system that allows for an evolutionary introduction of depth perception into the existing 2D digital TV framework. The work is part of the European Information Society Technologies (IST) project “Advanced Three-Dimensional Television System Technologies” (ATTEST), an activity where industries, research centers and universities have joined forces to design a backwardscompatible, flexible and modular broadcast 3D-TV system, where all parts of the 3D processing chain are optimised to one another. This includes content creation, coding and transmission, display and research in human 3D perception, which be will used to guide the development process. The goals of the project comprise the development of a novel broadcast 3D camera, algorithms to convert existing 2D-video material into 3D, a 2Dcompatible coding and transmission scheme for 3D-video using MPEG2/4/7 technologies and the design of two new autostereoscopic displays.

IST project ATTEST - an evolutionary and optimised approach on 3D-TV

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high-k Nb2O5–Bi2O3–MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high-k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si–BMN–ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 104, and the threshold voltage is ∼1.3 V, with over 200 cm2/(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that th...

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

Due to the untiring efforts of scientists and researchers on oxide semiconductor materials, processes, and devices, the applications for oxide-based thin film transistors (TFTs) have been researched and promoted on a large scale. With the advantages of relatively high carrier mobility, low off-current, good process compatibility, optical transparency, low cost, and especially flexibility, oxide-based TFTs have already been adapted for not only displays (e.g., liquid crystal display (LCD), organic light emitting diode (OLED), micro-light-emitting diode (Micro-LED), virtual reality/augmented reality (VR/AR) and electronic paper displays (EPD)) but also large-area electronics, analog circuits, and digital circuits. Furthermore, as the requirement of TFT technology increases, low temperature poly-silicon and oxide (LTPO) TFTs, which combine p-type LTPS and n-type oxide TFT on the same substrate, have drawn further interest for realizing the hybrid complementary metal oxide semiconductor (CMOS) circuit. This invited review provides the current progress on applications of oxide-based TFTs. Typical device configurations of TFTs are first described. Then, the strategies to apply oxide-based TFTs for improving the display quality with different compensation technologies and obtaining higher performance integrated circuits are highlighted. Finally, an outlook for the future development of oxide-based TFTs is given.

/pdf/strategies-for-applications-of-oxide-based-thin-film-2dhhyvly.pdf

Strategies for Applications of Oxide-Based Thin Film Transistors

The three-moduli set {2n,2n − 1,2n+ 1 − 1} started to receive more attention lately. This moduli set is considered an arithmetic-friendly set because it avoids the demanding channel (2n + 1) of the traditional 3-moduli set {2n,2n − 1,2n + 1}. This work considers an enhanced form of the above moduli set, {2n + k,2n − 1,2n+ 1 − 1}, and proposes a sign identifier for numbers within the dynamic range of the set. While the published sign identifiers have dealt with the unextended form {2n,2n − 1,2n+ 1 − 1}, this is the first sign identifier that deals with the extended form. Based on VLSI layout synthesis for the case (k = 0), the proposed structure has less or similar area and power requirements, nevertheless, it achieves an improved time performance in the range of (13.0–29.6)% compared with the most recent sign identifiers. When compared with a recently published residue-to-binary converter for the moduli set {2n + k,2n − 1,2n− 1 − 1}, which can function as a converter-based sign identifier, the proposed detector has on average reduced area, time, and power by 175%, 106%, and 60%, respectively.

Sign Identifier for the Enhanced Three Moduli Set {2 n + k , 2 n − 1, 2 n+ 1 − 1}

This paper proposes a unified and programmable crypto-processor with coarse-grained reconfigurable datapath to perform either RSA or elliptic curve cryptosystems (ECC) over prime field GF(p), which uses Residue Number System (RNS) as basic arithmetic to exploit data-level parallelism and Transport Triggered Architecture to improve instruction-level parallelism. The reconfigurable datapath provides three configuration modes to accelerate the RNS Montgomery multiplication(RNSMM). An efficient RNS base, 2n − ci, is chosen to reduce the multiplication complexity of RNSMM. Experimental results show that the proposed processor has better tradeoff among algorithm flexibility, performance and area than other related works.

A Unified Cryptographic Processor for RSA and ECC in RNS

This paper describes the design and fabrication of flexible radio-frequency inductors integrated on a polyethylene terephthalate substrate. Experimental and modeling results for the RF responses of flexible inductors are reported. Investigations and analysis have been conducted on the effects of layout and process parameters on the frequency responses of inductance, quality factor and self-resonant frequency of the spiral inductors. The influence of bending strain on the performance of spiral inductors is also investigated based on measurement and modeling results. The analysis provides guidelines for designing the flexible spiral inductors towards the flexible monolithic microwave integrated circuits on a plastic substrate.

Characterization of flexible radio-frequency spiral inductors on a plastic substrate

A low cost embedded auto-stereoscopic game conversion system is presented in this paper. The system is implemented both in software and hardware. The software is run on embedded GPU (E-GPU) to generate the depth map from a traditional 3D game which only has 2D images by extracting and processing the hidden information which is used to build the scene. Then multi-view image is generated by depth image based rendering (DIBR) accelerator which is implemented by hardware. To improve the efficiency, the parallel and pipelined architecture is proposed. The design is verified on FPGA platform. The result shows that the proposed system can convert traditional 3D game to stereoscopic game with low cost and low power. Therefore it is suitable for hand-held devices.

An Efficient Stereoscopic Game Conversion System for Embedded Platform

Flexible radio frequency (RF) circuits are highly desirable for flexible communication and other miniaturized function modules. However, the prevalent studies on flexible high-speed electronics have mostly focused on individual elements such as transistors, inductors, capacitors and transmission lines. Research on flexible RF monolithic integrated functional circuits is still limited. This letter presents the design of a flexible monolithic integrated silicon RF low noise amplifier (LNA) on plastic substrate. For the LNA, a flexible thin film transistor (TFT) based on a silicon nanomembrane, high-frequency flexible inductors and capacitors are fabricated and modeled. The impedance matching circuit on plastic substrate is analyzed and optimized. The LNA has a gain of ∼11 dB and a noise figure (NF) of ∼4.3 dB at 300 MHz. The influence of the parasitics induced by the flexible impedance matching on the gain and NF is discussed. This study provides useful design guideline for flexible RF monolithic integrated circuits and expands the high frequency applications of flexible electronics.

https://iopscience.iop.org/article/10.1088/1361-6463/abd05f/pdf

Hao Liu

Papers

A Unified Cryptographic Processor for RSA and ECC in RNS

Characterization of flexible radio-frequency spiral inductors on a plastic substrate

An Efficient Stereoscopic Game Conversion System for Embedded Platform

A flexible monolithic integrated silicon low noise amplifier on plastic substrate

On the performance characterization of silicon MOSFETs on 4° off-axis substrate