The invention discloses a method for filtering signal glitches based on a digital circuit, which at least comprises the following steps of performing delay processing on a signal to be filtered through a delay device chain to obtain a delay signal of the signal to be filtered; receiving the delay signal through an AND gate and an NOR gate, and outputting an output signal of the AND gate and an output signal of the NOR gate according to the delay signal; outputting a filtering result signal of the to-be-filtered signal according to the output signal of the AND gate and the output signal of theNOR gate; and filtering the delay signal according to the filtering result signal, and filtering glitches in the to-be-filtered signal. According to the method for filtering the signal glitches basedon the digital circuit, low-level glitches and high-level glitches in the signals can be effectively filtered out on the premise that the power consumption of the system is effectively reduced, and therefore the working stability of a chip can be effectively improved.

Method for filtering signal glitches in digital circuit

The invention discloses a high-frequency offline driver, which comprises a main driving circuit, a de-emphasis driving circuit, a first processing circuit, a signal generating circuit and a second processing circuit, wherein the first processing circuit is used for carrying out reverse phase delay processing on an input signal to obtain a reverse phase delay signal; the signal generation circuit is used for generating a switch control signal; the second processing circuit is used for carrying out logic processing on the anti-phase delay signal and the switch control signal; and obtaining a de-emphasis control signal, the de-emphasis control signal controlling the de-emphasis drive circuit to stop driving in a data invalid stage, and the de-emphasis control signal controlling the de-emphasis drive circuit to drive in a data valid stage According to the high-frequency offline driver provided by the invention, the circuit power consumption generated by the electric leakage path can be reduced

High-frequency offline driver

The invention belongs to the technical field of information security, and relates to secure storage of a nonvolatile memory, in particular to a device for evaluating data residues of the nonvolatile memory in a single-chip microcomputer. The method comprises the following steps: firstly, obtaining a physical structure and a use material of a nonvolatile memory to be tested through SEM section scanning, and performing simulating to obtain a relationship between floating gate charge Q and threshold voltage Vth according to physical structure parameters obtained by scanning and semiconductor characteristic parameters corresponding to the use material; then, obtaining the threshold voltage through chip reset interruption and a power-down method, and obtaining the change relation of the threshold voltage along with time in the erasing and writing process of the nonvolatile storage unit in the single-chip microcomputer; and finally, obtaining a relation curve between the sum Q0 + Qr of the injected charge and the residual charge on the floating gate and the erasure frequency N by using a charge injection and power failure method and combining the relation between the charge Q of the floating gate and the threshold voltage Vth according to the previously obtained change relation of the threshold voltage along with the time in the erasure process.

Device for evaluating data residues of nonvolatile memory in single-chip microcomputer

The invention discloses a low voltage detection circuit provided with a built-in MCU and having a voltage detection point dynamic switching function. The low voltage detection circuit includes a resistor R3 of which one end is grounded and the other end is connected in parallel with a resistor R2 and the drain of an MOS transistor N1. The source of the MOS transistor N1and the other end of the resistor R2 are connected in parallel with a resistor R1 and the out-of-phase input end of an operational amplifier. The in-phase input port of the operational amplifier is connected with a reference voltage Vref. The gate of the MOS transistor N1 is connected in series with the output end of INV1. The other end of the operational amplifier is connected in series with a trigger T1. The other end of the trigger T1 is connected in parallel with the input end of a delay unit DL1 and the input end of INV1 through N groups of triggers D. The reuse of a voltage detection module is realized. One voltagedetection module can achieve the functions of low voltage interruption and low voltage reset. Under the condition of guaranteeing the functions, the area of the chip is saved, and the static power consumption of the circuit is reduced.

Low voltage detection circuit provided with built-in MCU and having voltage detection point dynamic switching function

The invention relates to the field of manufacturing of a semiconductor integrated circuit and especially relates to a process design for a schottky diode. The schottky diode comprises a semiconductor substrate, an epitaxial layer, channels, gate medium layers, polycrystalline silicon, a schottky contact metal, a front metal layer and a back metal layer, wherein the epitaxial layer is arranged on the upper surface of the semiconductor substrate; the channels are arranged at the two ends of the epitaxial layer; the gate medium layers are arranged on the inner surfaces of the channels; the polycrystalline silicon is respectively arranged in the channels; the schottky contact metal is arranged on the upper surface of the epitaxial layer; the front metal layer is arranged on the upper surface of the schottky contact metal; the back metal layer is arranged on the surface on one side of the semiconductor substrate. According to the process design, SILVACO TCAD is utilized to perform structure and electric property modeling on the schottky diode, so that the model parameters influencing the withstanding voltage and current of the schottky diode are confirmed; the parameters are continuously adjusted and optimized according to a control variable method, so that the breakdown and reliability of the schottky diode can achieve the optimal combination; the development period can be further shortened and the yield can be increased.

Process design for schottky diode

The invention discloses an automatic reset structure for a clock switching process, comprising a time delay unit D, an exclusive-Or gate XOR, a first inverter INV1 and a second inverter INV2, an AND gate AND, a counter CT and a RS flip flop FF. The time delay unit D and the exclusive-Or gate XOR form a high level pulse generation circuit, and the high level pulse generation circuit is used for providing a clear signal of an asynchronous clear end Clr of the counter CT and a setting signal of a setting end S of the RS flip flop FF so as to generate a high level Rst reset signal; the first inverter INV1, the second inverter INV2 and the AND gate AND form a gated clock structure, and the gated clock structure is used for controlling a clock signal input by a clock input end CP of the counter CT; and when an output top digit QD of the counter CT outputs high level, the RS flip flop FF resets, and the Rst reset signal is removed. The automatic reset structure for the clock switching process can automatically output the reset signal when a clock selection signal changes; and when clock switching is completed, the automatic reset structure for the clock switching process automatically removes the reset signal, and thus, a controlled circuit is enabled to work normally.

Automatic reset structure for clock switching process

The invention discloses a method for reducing data remanence in a nonvolatile memory. The method comprises the steps of: carrying out structural modeling and electrical characteristic modeling on a non-volatile memory cell by Silvaco TCAD; determining model parameters corresponding to the factors affecting the data remanence in the non-volatile memory in a structural model and an electrical characteristic model; by use of the control variate method, determining the influence of any influence factor on the data remanence in the non-volatile memory according to a 0.18micron standard CMOS technology and calculating the quantity of floating gate electrons corresponding to floating gate charges; and reducing the quantity of the floating gate electrons by reducing the thickness of a tunnel oxide layer or increasing source voltage in an erasure operation or prolonging the erasure operation time, and selecting a model parameter value of the minimum quantity of the floating gate electrons to apply to the technical manufacturing process and the working process of a device, so that an attacker guesses stored data more difficultly according to the quantity of the floating gate electrons, namely the probability of restoring the data is effectively reduced.

He Jiaji

Papers

Automatic reset structure for clock switching process

Method for reducing data remanence in nonvolatile memory