The invention relates to the chip focusing resistance ion beam attack field and provides a top metal protection layer integrity detection method based on a sigma-delta modulator. In the method, through detecting whether a resistance value of a metal line is changed, whether a protection layer is complete is detected and then whether an attacker uses FIB to correct the protection layer is determined. A chip top protection layer integrity detection apparatus is formed by a top metal line AB, operation amplifiers AMP and AMP1, PMOS pipes M1 and M2, an NMOS pipe M3, switches S1 and S2, a reference current source I, a comparator COMP with a clock terminal, a counter CT and a digital comparator DCMP. The apparatus is mainly applied to a chip focusing resistance ion beam attack occasion.

Chip top protection layer integrity detection apparatus

The embodiment of the invention provides a light intensity detection unit and a light intensity detector, as well as a detection method and display device thereof, relates to the technical field of display, and aims to solve the problem of reduced detection accuracy due to poor amplitude noise resistance in the process of collecting the amplitude of a photoelectric current signal generated by a photosensitive device. The light intensity detection unit comprises a first reverser, a second reverser, a third reverser, a photosensitive device and an energy storage module, wherein the first reverser is used for respectively outputting voltage of a first voltage terminal and voltage of a second voltage terminal to the energy storage module under control of the signal input end of the light intensity detection unit; the second reverser and the third reverser are used for controlling the photo-current generated by the photosensitive device to output along the first direction and the second direction; and the energy storage module is used for controlling the voltage of the signal output end of the light intensity detection unit by voltage storage or voltage release.

Light intensity detection unit and light intensity detector, as well as detection method and display device thereof

The invention relates to a polarization interference device of optical path self-coupling and a matching method. The method comprises a step of establishing a rectangular coordinate system with a Y axis which is perpendicular to a paper face, an X axis which is parallel to the paper surface, and a Z axis which is the spreading direction of light, and a step of orderly arranging a light source, a first off-axis parabolic mirror, a polarizer, a compensation crystal, a fixed crystal optical wedge, a scanning crystal optical wedge, an analyzer , a second off-axis parabolic mirror, a filter and a detector along an optical path direction. The invention provides a polarization interference device which improves luminous flux and the modulation of an interference signal and a matching method thereof.

Optical path self-coupling method, polarization interference device, and polarization interference matching method

The invention discloses a method for filtering signal glitches based on a digital circuit, which at least comprises the following steps of performing delay processing on a signal to be filtered through a delay device chain to obtain a delay signal of the signal to be filtered; receiving the delay signal through an AND gate and an NOR gate, and outputting an output signal of the AND gate and an output signal of the NOR gate according to the delay signal; outputting a filtering result signal of the to-be-filtered signal according to the output signal of the AND gate and the output signal of theNOR gate; and filtering the delay signal according to the filtering result signal, and filtering glitches in the to-be-filtered signal. According to the method for filtering the signal glitches basedon the digital circuit, low-level glitches and high-level glitches in the signals can be effectively filtered out on the premise that the power consumption of the system is effectively reduced, and therefore the working stability of a chip can be effectively improved.

Method for filtering signal glitches in digital circuit

The invention relates to the field of chip technology and information safety. By the method, the wiring density of a metal wire at a top layer can be improved, the failure area of a shielding line ata key region is reduced, the difficulty on circuit analysis by an attacker is improved, the purpose of important protection on the key region of the chip is achieved, the attacker can be effectively prevented from acquiring internal data of the chip by attack means such as shooting analysis reverse engineering and FIB, and a safety coefficient of the key region of the chip is improved. The wiringmethod for reinforcing protection on the important region of the metal protection layer at the top layer of the chip, disclosed by the technical scheme comprises the steps of firstly, planning wiringregion area and a protection level of each region according to the size of the chip, and dividing a metal shielding layer at the top layer into several wiring regions; and secondly, wiring and fillingeach wiring unit according to a safety coefficient of the wiring region, wherein the wiring number of each region is gradually increased according to the safety level. The method is mainly applied toa chip design and manufacturing occasion.

Wiring method for reinforcing protection on important region of metal protection layer at top layer of chip

The invention discloses a reconstruction method for a top metal protection layer of a chip. Through the random reconstruction of a wiring layer, the safety protection level of the top metal protection layer of the chip is increased. The reconstruction method for the top metal protection layer of the chip comprises the following steps of step I, generating Hamiltonian loop wiring units by utilizing a random Hamiltonian loop way, wherein each wiring unit is of a Hamiltonian loop graphical structure; according to the integration degree level of the chip, determining the area of each wiring unit and the number of the wiring units contained in the wiring layer; a step II, as each wiring unit is provided with a connecting port, splicing a plurality of wiring units to form minimum reconstruction units by means of the random connection of different ports among the plurality of wiring units, so as to form a basic unit for realizing the random reconstruction of the integral wiring layer; a step III, splicing and nesting the minimum reconstruction units in sequence, and realizing the dynamic random reconstruction of the integral wiring layer by utilizing the random switching of a connection relation of the minimum reconstruction units.

Reconstruction method for top metal protection layer of chip

The invention discloses an automatic reset structure for a clock switching process, comprising a time delay unit D, an exclusive-Or gate XOR, a first inverter INV1 and a second inverter INV2, an AND gate AND, a counter CT and a RS flip flop FF. The time delay unit D and the exclusive-Or gate XOR form a high level pulse generation circuit, and the high level pulse generation circuit is used for providing a clear signal of an asynchronous clear end Clr of the counter CT and a setting signal of a setting end S of the RS flip flop FF so as to generate a high level Rst reset signal; the first inverter INV1, the second inverter INV2 and the AND gate AND form a gated clock structure, and the gated clock structure is used for controlling a clock signal input by a clock input end CP of the counter CT; and when an output top digit QD of the counter CT outputs high level, the RS flip flop FF resets, and the Rst reset signal is removed. The automatic reset structure for the clock switching process can automatically output the reset signal when a clock selection signal changes; and when clock switching is completed, the automatic reset structure for the clock switching process automatically removes the reset signal, and thus, a controlled circuit is enabled to work normally.

Automatic reset structure for clock switching process

The invention belongs to the field of optical detection, and particularly relates to a capacitive trans-impedance amplifier circuit with pure digital output for weak light detection. The capacitive trans-impedance amplifier circuit comprises a signal generating circuit, a CTIA-based optical detecting circuit and a two-stage inverter; and furthermore the signal generating circuit, the CTIA-based optical detecting circuit and the two-stage inverter are successively connected. The signal generating circuit comprises a sampling signal SELECT circuit and a square wave reset signal RESET circuit. An original square wave signal is input into the input end of the sampling signal SELECT circuit. The original square wave signal is transmitted to a first delay unit and then is transmitted to one input end of an XOR gate, and the original square wave signal is input to the other input end of the XOR gate. AND operation between the pulse signal which is output from the XOR gate and the original square wave signal is performed for obtaining a sampling signal SELECT. The square wave reset signal RESET is obtained from the original square wave signal through a three-stage delay unit. The capacitive trans-impedance amplifier circuit is advantageous in that pure digital output can be realized in detecting the weak light, thereby facilitating processing by a following circuit.

Capacitive trans-impedance amplifier circuit with pure digital output for weak light detection

The invention discloses a method for reducing data remanence in a nonvolatile memory. The method comprises the steps of: carrying out structural modeling and electrical characteristic modeling on a non-volatile memory cell by Silvaco TCAD; determining model parameters corresponding to the factors affecting the data remanence in the non-volatile memory in a structural model and an electrical characteristic model; by use of the control variate method, determining the influence of any influence factor on the data remanence in the non-volatile memory according to a 0.18micron standard CMOS technology and calculating the quantity of floating gate electrons corresponding to floating gate charges; and reducing the quantity of the floating gate electrons by reducing the thickness of a tunnel oxide layer or increasing source voltage in an erasure operation or prolonging the erasure operation time, and selecting a model parameter value of the minimum quantity of the floating gate electrons to apply to the technical manufacturing process and the working process of a device, so that an attacker guesses stored data more difficultly according to the quantity of the floating gate electrons, namely the probability of restoring the data is effectively reduced.

Method for reducing data remanence in nonvolatile memory

The invention discloses a high-frequency clock frequency detection structure circuit for resisting an attack chip The circuit comprises two D triggers which are connected in series and are triggered by a rising edge, three two-input AND gate, a delay unit D, an OR gate, a 10-bit asynchronous reset binary addition counter CT, a 10-bit latch and a 10-bit digital comparer DCMP The two D triggers which are triggered by the rising edge, and the three two-input AND gate form a gate control clock structure The delay unit D is formed by connecting the even number of phase inverters in series Delay time is controlled by adjusting the number of the phase inverters Two 10-bit registers, a frequency upper limit register H and a frequency lower limit register L, are contained in the10-bit digital comparer DCMP The delay unit D or the OR gate forms a delay reset structure An internal low-frequency clock is taken as a counting gate, the number of high-frequency clock periods is counted in fixed time, and the high-frequency clock frequency is deduced When the obtained frequency exceeds a normal working frequency range, an alarm signal is generated

Zhao Yiqiang

Papers

Reconstruction method for top metal protection layer of chip

Automatic reset structure for clock switching process

Capacitive trans-impedance amplifier circuit with pure digital output for weak light detection

Method for reducing data remanence in nonvolatile memory

High-frequency clock frequency detection structure for resisting attack chip