Patent
Automatic reset structure for clock switching process
TLDR
In this paper, an automatic reset structure for a clock switching process, comprising a time delay unit D, an exclusive-Or gate XOR, a first inverter INV1 and a second inverter INV2, an AND gate AND, a counter CT and a RS flip flop FF, was presented.Abstract:
The invention discloses an automatic reset structure for a clock switching process, comprising a time delay unit D, an exclusive-Or gate XOR, a first inverter INV1 and a second inverter INV2, an AND gate AND, a counter CT and a RS flip flop FF. The time delay unit D and the exclusive-Or gate XOR form a high level pulse generation circuit, and the high level pulse generation circuit is used for providing a clear signal of an asynchronous clear end Clr of the counter CT and a setting signal of a setting end S of the RS flip flop FF so as to generate a high level Rst reset signal; the first inverter INV1, the second inverter INV2 and the AND gate AND form a gated clock structure, and the gated clock structure is used for controlling a clock signal input by a clock input end CP of the counter CT; and when an output top digit QD of the counter CT outputs high level, the RS flip flop FF resets, and the Rst reset signal is removed. The automatic reset structure for the clock switching process can automatically output the reset signal when a clock selection signal changes; and when clock switching is completed, the automatic reset structure for the clock switching process automatically removes the reset signal, and thus, a controlled circuit is enabled to work normally.read more
Citations
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References
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Patent
Clock switching circuit
TL;DR: In this article, a clock switching circuit, comprising a first level trigger, a second level logic circuit and a third level data selector, was disclosed by the utility model, which has the advantages of simple hardware structure, flexible configuration and stable performance.
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TL;DR: In this paper, the clock loss detection has two edge detection circuits and a clock loss detect counter circuit, each edge detection circuit includes a reset signal circuit that generates reset signal in response to a transition of a clock signal.
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TL;DR: In this paper, a multi-clock switchover circuit consisting of a clock switchover module, a synchronous control module, and a door control module is described, which is capable of simplifying digital control.