A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Post passivation interconnection schemes on top of the ic chips

A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined

Semiconductor integrated circuit device

The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance with an internal signal. The area of the terminating circuit is reduced while the reliability against the surge is maintained. Thus, an output circuit containing the terminating circuit that occupies a small area and is capable of transmitting a signal/data at high speed is provided.

Semiconductor device with bus terminating function

The magnitude of an amplitude waveform of an electromagnetic wave generated when irradiating a pulse laser beam to a structure A including diffusion regions provided in the structure of a semiconductor device to be inspected is compared with the magnitude of an amplitude waveform of an electromagnetic wave radiated when irradiating the pulse laser beam to a structure A of a reference device measured in advance, and the detection sensitivity of the electromagnetic wave is corrected (S14). Thereafter, measurement errors caused by variations in the detection sensitivity of electromagnetic waves of an inspecting apparatus are eliminated by inspecting the semiconductor device as an inspection target, so that the quality of the semiconductor device is precisely determined (S16).

Method and apparatus for inspecting semiconductor device

PROBLEM TO BE SOLVED: To improve the driving capability of a semiconductor device having a trench structure SOLUTION: The trench 10 to form concavity and convexity in a well 5 in a gate width direction is formed in the well 5 of the semiconductor device A gate electrode 2 is formed in inner and upper surface portions of the trench 10 through an insulating film 7 A source region 3 is formed in one side of the gate length direction of the gate electrode 2, and a drain region 4 is disposed in the other side thereof Further, the source region 3 and drain region 4 are all formed into the depth adjacent to the bottom of the gate electrode 2 (adjacent to the bottom of the trench 10) Thus, a current dominantly flowed to a shallow portion of the gate electrode 2 is uniformly supplied to the entire part of the trench 10 by forming the source region 3 and drain region 4 deeply into the bottom, so that the effective gate width expansion is achieved by the concavity and convexity formed in the well 5 This allows the semiconductor device 1 to reduce the on-state resistance and enhance the driving capability COPYRIGHT: (C)2008,JPO&INPIT

Semiconductor device and method of manufacturing same

PROBLEM TO BE SOLVED: To reduce the size of a chip by making first minimum distance between a channel widthwise direction end portion of a drain region of an MOS transistor and a contact region end portion larger than second minimum distance between a gate electrode side end portion in the channel lengthwise direction of the drain region and the contact region end portion. SOLUTION: First minimum distance 21 between a channel widthwise direction end portion of a drain region 10 and an end portion of a contact region 12 electrically connecting the drain region 10 and a metal electrode 14, is made larger than second minimum distance 22 between a gate electrode 11 side end portion in the channel lengthwise direction of the drain region 10 and the end portion of the contact region 12 electrically connecting the drain region 10 and the metal electrode 14. Localization of eddy current which is generated when electrostatic noise is applied to the drain region 10 is relieved, and breakdown of a transistor which is to be generated by local heat generation is restrained. As a result, electrostatic durability of a transistor for an I/O circuit can be increased, and reduction effect of manufacturing cost due to reduction of chip size is obtained. COPYRIGHT: (C)2000,JPO

Semiconductor integrated circuit device and manufacture thereof

PROBLEM TO BE SOLVED: To solve the problem of the N channel MOS transistor in a high breakdown voltage semiconductor element that although it has a heavily doped and deeply diffused drain structure, a desired breakdown voltage cannot be attained because of a parasitic NPN transistor being formed across the drain, the well and a semiconductor substrate SOLUTION: The semiconductor element comprises a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate and having an electric polarity identical to that of the semiconductor substrate, a buried diffusion layer formed between the semiconductor substrate and the epitaxial layer and having an electric polarity different from that of the semiconductor substrate, and an MOS transistor formed on the buried diffusion layer and having an electric polarity identical to that of the buried diffusion layer connected electrically with the well region Its fabricating method is also provided COPYRIGHT: (C)2003,JPO

Semiconductor element and its fabricating method

PROBLEM TO BE SOLVED: To provide a semiconductor wafer comprising a calibration element and a semiconductor device capable of calibrating, with accurate reproducibility, at the same measurement point as an actual semiconductor device, with no requirement for exchanging a board of the semiconductor inspection device. SOLUTION: A semiconductor inspection device can be calibrated under the same condition with measurement of the semiconductor device itself by integrating a reference resistor as a calibration element on the same semiconductor wafer as that, in which a semiconductor device measured using a semiconductor inspection device is formed. Since the calibration element is inside the semiconductor wafer, the board of the semiconductor inspection device is not required to be exchanged, and operation hours can be made efficient in the inspection device. COPYRIGHT: (C)2007,JPO&INPIT

Semiconductor wafer and calibration method of semiconductor inspection device using the same

PURPOSE:To make it possible to form a low-cost, high-performance and high- withstand voltage semiconductor integrated circuit as a high-withstand voltage MIS transistor can be formed on the same substrate along with a low-withstand voltage transistor of high-speed operation because the gate insulating film of the high-withstand voltage MIS transistor can be made thin. CONSTITUTION:A high-withstand voltage transistor 15 and a low-withstand voltage transistor 14 are formed on a P-type substrate and an N+ or - drain region 6 is formed between channel and N drain regions 7 of the transistor 15 for making it possible to form the film thickness of a gate oxide film 3 of the transistor 15 in a thickness equal with that of a gate oxide film 3 of the transistor 14.

High-withstand voltage insulated-gate type field-effect transistor and semiconductor integrated circuit device

PROBLEM TO BE SOLVED: To restrict an increase in circuit size even when printing with a plurality of gradations or in a plurality of colors is carried out by one heating resistor. SOLUTION: Two latch circuits 5r and 5b for red and black are used for two-color printing data. One shift register 4 is used in common for inputs of a red data r and a black data b to supply data to the latch circuits 5r and 5b. Since the shift register 4 is shared, one shift register 4 will do for two-color printing and a chip can be made small. In using the integrated circuit for driving a thermal head, inputs of the read data r and black data b are alternately input from a control terminal SI and a corresponding latch signal is input after 64 bits of each color data are completely input, thereby enabling two-color printing (setting).

和敏石井

Papers

Semiconductor integrated circuit device and manufacture thereof

Semiconductor element and its fabricating method

Semiconductor wafer and calibration method of semiconductor inspection device using the same

High-withstand voltage insulated-gate type field-effect transistor and semiconductor integrated circuit device

Integrated circuit for driving thermal head

和敏 石井

Papers

Semiconductor integrated circuit device and manufacture thereof

Semiconductor element and its fabricating method

Semiconductor wafer and calibration method of semiconductor inspection device using the same

High-withstand voltage insulated-gate type field-effect transistor and semiconductor integrated circuit device

Integrated circuit for driving thermal head

和敏石井